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1 222 Commity
17 Gałęzie
93 Tagi
20 MiB
Wykres commitów

84 Commity (ec04f8ce5309195f10e523b414df05ebbd36d665)

Autor SHA1 Wiadomość Data
IanSB 168c617b25 Update RGB CPLD to inhibit clamp pulse in DC mode 2020-06-23 05:46:40 +01:00
IanSB 09533978ee Fix CPLD issue 2020-02-23 06:39:37 +00:00
IanSB 743a665a30 Update RGB cpld with sync on green support 2020-02-22 18:53:16 +00:00
David Banks 1341539945 CPLD: cosmetic renaming, no change to jedec files 
Change-Id: Icb26a3fc735ae493a6fc363d3ddf05f534bea7e2
 2020-02-08 12:41:24 +00:00
David Banks 7c5ad6db84 BBC CPLD v6.6 rebuilt; RGB CPLD v7.2: remove swap_bits 
Change-Id: I31d42895028465890f672212133d52abcb1eaa27
 2020-02-08 12:41:24 +00:00
David Banks 7150fee0d0 VHDL: properly isolate analog additions (now v6.6 as mono on vsync dropped) 
Change-Id: Ibe623728d4dee39672fd533c3ee3ff8fa2fd93c6
 2019-12-22 16:22:18 +00:00
David Banks 850703474c VHDL: formatting only, remove tabs 
Change-Id: I3123b5ab7751c95953b5b5dd889c50c120324b95
 2019-12-22 15:30:38 +00:00
IanSB 9076eb238b Update common VHDL with support for new RGB/YUV board (RGB7.1 / YUV3.1) 2019-12-17 02:35:04 +00:00
David Banks 98170366a5 Refactor xilinx projects so vhdl_bbc and vhdl_RGB_6bit share same vhdl/ucf file 
Change-Id: I7c6db57f6b1fe8331dbeaacc81e49e8239349625
 2019-12-05 14:34:59 +00:00
IanSB c3d1ac43de Update CPLD to v6.5: Add new mux option in 6 bit mode using the Vsync input for monochrome video 2019-11-10 02:30:51 +00:00
David Banks 3b58d05cdd CPLD: Updated fitting notes for v6.4 
Change-Id: I56c96e0155cbc44e7bd820aeb3f9f3c1c7797d3c
 2019-04-04 14:08:10 +01:00
IanSB c2d17bfe94 CPLD V6.4 separate vsync 2019-04-03 20:32:22 +01:00
David Banks b2436c6ffd CPLD: Updated fitting notes for v6.3 
Change-Id: Ie4195034fd00e569bf14284b3ac7797a7118b9bd
 2019-03-31 18:01:16 +01:00
IanSB 01ccdbded8 Binary .jed for CPLD v6.3 2019-03-31 16:26:40 +01:00
IanSB 3b9df23f84 CPLD v6.3 send csync2 to Pi and change csync to psync delay 2019-03-27 02:23:53 +00:00
David Banks 6778315345 CPLD: Fixed a bug with half-pixel delay (now v6.2) 
Change-Id: I110ba7cb322438801aa26ce51a933a1d7d40804c
 2019-03-24 12:11:12 +00:00
David Banks 58fb277106 CPLD: Increased counter from 7 back to 8 bits (now v6.1) 
Change-Id: Ia803625db0b88204f41de3f81ba5d870d1ea1e40
 2019-03-24 08:42:36 +00:00
David Banks 989d098b32 Delay reduced to 2 bits plus psync changes (now v6.0) 
Change-Id: Ie84ecd1556d796a8edd9080d14ec0e8acbefdd16
 2019-03-23 18:33:53 +00:00
David Banks a2d5ed5722 CPLD: Added sync invert function (now v5.0) 
Change-Id: Ie1701c5ba25e198e741cb51ce87b33e708b415f1
 2019-03-14 18:10:30 +00:00
David Banks a03b884f3e CPLD: Reverted: Align quad timing back to cycle 0 as before (issues at offset 0) 
Change-Id: I83aa6f555695a1cd5a607e676a4b110cfdbf35e9
 2019-03-13 13:57:51 +00:00
David Banks ecc5813441 CPLD: Fix long-standing bug concerning offset selection in Mode 0..6 
Change-Id: I463f8d8994c365bbbb8d6d8c1ff2804401fc3380
 2019-03-12 22:42:09 +00:00
David Banks 55e5d8f683 CPLD: Align quad timing back to cycle 0 as before 
Change-Id: I0dd0504670f8e79f8139bc5f38bd7f8af52b8950
 2019-03-12 22:32:08 +00:00
David Banks a58cd27837 CPLD: Optimize generation of PSync, and allow more skew 
Change-Id: Id63a46a5cd909fd22445573666010a635e24a433
 2019-03-12 21:31:11 +00:00
David Banks b4f808ee0d CPLD: Added half-odd and half-even sampling (now v4.0) 
Change-Id: Ie349def5dacf1fe73cc15199c3cf4607e2332e7a
 2019-03-12 18:47:29 +00:00
David Banks 4b27164f3c CPLD: Added one cycle of skew to PSYNC 
Change-Id: I18b668e70c148781a5215b55a4e009760984855b
 2019-03-08 18:32:41 +00:00
David Banks d568b3be96 CPLD: Allow PSYNC duty cycle to be asymmetric 
Change-Id: I28bc639a496c845637998303b4d6e29a1dc0bbdf
 2019-03-08 16:22:19 +00:00
David Banks f906cf98a0 CPLD: Halt the counter during HSYNC 
Change-Id: I54d97c22572218a341e74f4bd861dfcbe66a0043
 2019-03-08 16:20:38 +00:00
David Banks 8a21efe080 CPLD: Re-order bits when rate=1 
Change-Id: Iee51a1916c47d95d4683578836f4c1b6f531e8b8
 2019-03-08 13:49:25 +00:00
David Banks 30d1cec731 Implement rate bit to support double rate (6 bits/pixel) sampling 
Change-Id: I324b9ea804f449e208361071d5081d28f9acf85d
 2019-03-08 11:39:57 +00:00
David Banks 0b74c3fdd3 CPLD: Reduced counter from 12 to 8 bits, and trigger of rising edge of HSYNC 
Change-Id: If1ccc236b5fc7e55c0eb278500a06671b32dc83c
 2019-03-08 11:14:59 +00:00
David Banks 31ac05cd1e CPLD: Make counter_type a seperate type (no logical change) 
Change-Id: Ieb022a9d96854c98acc8e01c7244188ac56dca92
 2019-03-08 11:14:59 +00:00
David Banks d5a13e0077 CPLD: Updated fitting notes and .jed file with v2.3 
Change-Id: I7a258df7f5f8b9610f8ef24242fbec24ec2f11ec
 2019-03-08 11:14:59 +00:00
IanSB b5b6c7a880 Add separate H and V sync support to CPLD 2019-03-06 02:29:27 +00:00
David Banks 17b6673b13 CPLD: Correct issue with delay in 6 clocks/pixel mode 
Change-Id: I55c2e8bf34a31d5fcbc2559d9ebc7af7257a71ec
 2019-02-25 19:57:29 +00:00
David Banks cb5a8461b6 CPLD: Start sampling 8us earlier 
Change-Id: I0f1215f801f46472597130476e8912a25bf00e38
 2018-11-11 17:20:58 +00:00
David Banks 035381c1fc CPLD: Increment to version 2.0 and update checked-in .jed file 
Change-Id: I58fe111c1bf969abe7692cffacd7d20a73647df6
 2018-10-29 15:27:31 +00:00
David Banks 8658dfc9cc CPLD: Make bits 7..4 of the MODE 7 offset counter programmable 
Change-Id: Icc44f2b90d27548559283236f8a7df749d817d4b
 2018-10-29 15:26:16 +00:00
David Banks 5d7839ec84 CPLD: Re-centred MODE 7 screen 
Change-Id: I70d8d27c773cddb849985c7ead85a71faaf8ed8b
 2018-10-25 11:01:36 +01:00
David Banks a546d6bd42 CPLD: Updated released .jed file to v1.1 
Change-Id: I2bdeddc68e3e3606425bae5d779a8db7729a8dac
 2018-10-16 15:53:52 +01:00
David Banks 7369f6416f CPLD: Reduce csync de-glitch counter to 2 bits 
Change-Id: I5752c6f15cc8c69a656187a9c94d5172df276586
 2018-10-15 21:58:42 +01:00
David Banks a91f915022 CPLD: De-glitch both states of csync 
Change-Id: Id0ad7dca9ab36fc39bef246896c2f4fcc9a34cc1
 2018-10-15 20:53:12 +01:00
David Banks 4c9a79cc01 CPLD: increased de-glitching (IanB's issue) but still unresolved 
Change-Id: I255bdba7d2b42d5078b3e4d616c3b1deee9ca466
 2018-10-15 16:19:23 +01:00
David Banks 54bba7c5e1 Added JEDEC file for the 1.0 release 
Change-Id: I78e6c0897c3825954e9a9a5ec4b9b676323d24eb
 2018-09-23 12:38:00 +01:00
David Banks b2ed64acee CPLD: Start counting off leading edge of HSYNC 
Change-Id: I3c1baa29f3db2183ce6920870bcb4e7c936c1b6b
 2018-07-15 15:36:02 +01:00
David Banks 6982b3149a CPLD: Corrected sampling offset to better centre screen; CPLD version now 0.9 
Change-Id: I2ef25e2bda982080329deaf6569299c695d7ee1d
 2018-07-15 15:31:51 +01:00
David Banks fc342ad0b0 Normal CPLD: de-glitch csync (needs to be low for 3 samples) 
Change-Id: I6d071cdd003536bc13dfa7fd24ede67a1a25d56c
 2018-06-22 11:45:05 +01:00
David Banks ae88d35ce7 CPLD: final pinout changes 
Change-Id: I8b18f9f4b3445a79b82b5667971725cb8636fe9a
 2018-06-12 12:39:06 +01:00
David Banks d49c1896fb CPLD: Juggled GPIO assignments so CPLD pin 33 (GSR) connects to GPIO18 (Version) 
Change-Id: I6ea4e6ad40d7eb4f785df31ae14a446e05a0be46
 2018-06-12 10:22:29 +01:00
David Banks 5383f60c29 CPLD: Added configurable half-pixel delay 
Change-Id: I98a708d4e6dd753198e8db7d4c03447a61557648
 2018-06-09 20:41:06 +01:00
David Banks c595278204 CPLD: Added version support to both CPLDs 
Change-Id: Ie2b0698a4ba523b392507349a37a6554daafbc0b
 2018-06-09 13:24:47 +01:00