kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
CPLD: Increased counter from 7 back to 8 bits (now v6.1)
Change-Id: Ia803625db0b88204f41de3f81ba5d870d1ea1e40pull/63/head
rodzic
d751cb8b23
commit
58fb277106
1554
vhdl/RGBtoHDMI.jed
1554
vhdl/RGBtoHDMI.jed
Plik diff jest za duży
Load Diff
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@ -50,11 +50,11 @@ end RGBtoHDMI;
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architecture Behavorial of RGBtoHDMI is
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subtype counter_type is unsigned(7 downto 0);
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subtype counter_type is unsigned(8 downto 0);
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-- Version number: Design_Major_Minor
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-- Design: 0 = Normal CPLD, 1 = Alternative CPLD
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constant VERSION_NUM : std_logic_vector(11 downto 0) := x"060";
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constant VERSION_NUM : std_logic_vector(11 downto 0) := x"061";
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-- Sampling points
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constant INIT_SAMPLING_POINTS : std_logic_vector(23 downto 0) := "000000011011011011011011";
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@ -180,7 +180,7 @@ begin
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-- reset counter on the rising edge of csync
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if last = '0' and csync2 = '1' then
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if rate(1) = '1' then
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counter(7 downto 3) <= "11" & delay & "0";
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counter(8 downto 3) <= "100" & delay & "0";
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if half = '1' then
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counter(2 downto 0) <= "000";
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elsif mode7 = '1' then
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@ -189,7 +189,7 @@ begin
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counter(2 downto 0) <= "100";
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end if;
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else
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counter(7 downto 3) <= "111" & delay;
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counter(8 downto 3) <= "1100" & delay;
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if half = '1' then
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counter(2 downto 0) <= "000";
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elsif mode7 = '1' then
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@ -547,3 +547,14 @@ FB3 18/18* 28/54 65/90 9/ 9*
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FB4 16/18 35/54 86/90 5/ 7
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----- ----- ----- -----
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70/72 127/216 248/360 29/34
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49. Increased counter from 7 back to 8 bits (now v6.1)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 41/54 65/90 7/ 9
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FB2 18/18* 23/54 37/90 8/ 9
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FB3 18/18* 28/54 65/90 9/ 9*
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FB4 17/18 34/54 88/90 5/ 7
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----- ----- ----- -----
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71/72 126/216 255/360 29/34
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