CPLD: Increased counter from 7 back to 8 bits (now v6.1)

Change-Id: Ia803625db0b88204f41de3f81ba5d870d1ea1e40
pull/63/head
David Banks 2019-03-24 08:42:36 +00:00
rodzic d751cb8b23
commit 58fb277106
3 zmienionych plików z 792 dodań i 781 usunięć

Plik diff jest za duży Load Diff

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@ -50,11 +50,11 @@ end RGBtoHDMI;
architecture Behavorial of RGBtoHDMI is
subtype counter_type is unsigned(7 downto 0);
subtype counter_type is unsigned(8 downto 0);
-- Version number: Design_Major_Minor
-- Design: 0 = Normal CPLD, 1 = Alternative CPLD
constant VERSION_NUM : std_logic_vector(11 downto 0) := x"060";
constant VERSION_NUM : std_logic_vector(11 downto 0) := x"061";
-- Sampling points
constant INIT_SAMPLING_POINTS : std_logic_vector(23 downto 0) := "000000011011011011011011";
@ -180,7 +180,7 @@ begin
-- reset counter on the rising edge of csync
if last = '0' and csync2 = '1' then
if rate(1) = '1' then
counter(7 downto 3) <= "11" & delay & "0";
counter(8 downto 3) <= "100" & delay & "0";
if half = '1' then
counter(2 downto 0) <= "000";
elsif mode7 = '1' then
@ -189,7 +189,7 @@ begin
counter(2 downto 0) <= "100";
end if;
else
counter(7 downto 3) <= "111" & delay;
counter(8 downto 3) <= "1100" & delay;
if half = '1' then
counter(2 downto 0) <= "000";
elsif mode7 = '1' then

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@ -547,3 +547,14 @@ FB3 18/18* 28/54 65/90 9/ 9*
FB4 16/18 35/54 86/90 5/ 7
----- ----- ----- -----
70/72 127/216 248/360 29/34
49. Increased counter from 7 back to 8 bits (now v6.1)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 41/54 65/90 7/ 9
FB2 18/18* 23/54 37/90 8/ 9
FB3 18/18* 28/54 65/90 9/ 9*
FB4 17/18 34/54 88/90 5/ 7
----- ----- ----- -----
71/72 126/216 255/360 29/34