kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
CPLD: Allow PSYNC duty cycle to be asymmetric
Change-Id: I28bc639a496c845637998303b4d6e29a1dc0bbdfpull/32/head
rodzic
f906cf98a0
commit
d568b3be96
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@ -286,7 +286,7 @@ begin
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quad <= VERSION_NUM;
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psync <= '0';
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elsif counter(counter'left) = '0' then
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if counter(3 downto 0) = "0000" and (rate = '1' or counter(4) = '0') then
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if counter(4 downto 0) = 0 or (rate = '1' and counter(4 downto 0) = 16) then
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quad(11) <= shift_B(3);
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quad(10) <= shift_G(3);
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quad(9) <= shift_R(3);
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@ -300,7 +300,7 @@ begin
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quad(1) <= shift_G(0);
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quad(0) <= shift_R(0);
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if rate = '1' then
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psync <= counter(4);
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psync <= counter(0) or counter(1) or counter(2) or counter(3) or counter(4);
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else
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psync <= counter(5);
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end if;
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@ -455,3 +455,14 @@ FB3 17/18 35/54 81/90 9/ 9*
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FB4 18/18* 39/54 65/90 5/ 7
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----- ----- ----- -----
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68/72 140/216 243/360 29/34
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41. Allow PSYNC duty cycle to be asymmetric
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 17/18 40/54 61/90 7/ 9
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FB2 16/18 26/54 36/90 8/ 9
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FB3 17/18 35/54 81/90 9/ 9*
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FB4 18/18* 39/54 65/90 5/ 7
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----- ----- ----- -----
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68/72 140/216 243/360 29/34
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