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RGBtoHDMI
kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
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CPLD: Added version support to both CPLDs 

Change-Id: Ie2b0698a4ba523b392507349a37a6554daafbc0b
issue_1022
David Banks 2018-06-09 13:24:47 +01:00
rodzic 29f8179a3a
commit c595278204
5 zmienionych plików z 45 dodań i 9 usunięć
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2
vhdl/RGBtoHDMI.ucf
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@ -22,11 +22,11 @@ NET "G1" LOC = "P36"; # input
NET "B1" LOC = "P37"; # input
NET "S" LOC = "P30"; # input
NET "version" LOC = "P7"; # input gpio0
NET "SW1" LOC = "P39"; # input gpio16
NET "SW2" LOC = "P40"; # input gpio26
NET "SW3" LOC = "P41"; # input gpio19
NET "link" LOC = "P42"; # input gpio25 (connects to link / test point)
NET "spare" LOC = "P7"; # input gpio0
NET "mode7" LOC = "P19"; # input gpio22
NET "elk" LOC = "P18"; # input gpio24

15
vhdl/RGBtoHDMI.vhdl
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@ -6,7 +6,7 @@
-- Project Name: RGBtoHDMI
-- Target Devices: XC9572XL
--
-- Version: 0.9
-- Version: 0.1
--
----------------------------------------------------------------------------------
library ieee;
@ -38,10 +38,10 @@ entity RGBtoHDMI is
csync: out std_logic;
-- User interface
SW1: in std_logic;
version: in std_logic;
SW1: in std_logic; -- currently unused
SW2: in std_logic; -- currently unused
SW3: in std_logic; -- currently unused
spare: in std_logic; -- currently unused
link: in std_logic; -- currently unused
LED1: out std_logic;
LED2: out std_logic
@ -50,6 +50,10 @@ end RGBtoHDMI;
architecture Behavorial of RGBtoHDMI is
-- Version number: Design_Major_Minor
-- Design: 0 = Normal CPLD, 1 = Alternative CPLD
constant VERSION_NUM : std_logic_vector(11 downto 0) := x"001";
-- For Modes 0..6
constant default_offset : unsigned(11 downto 0) := to_unsigned(4096 - 64 * 17 + 6, 12);
@ -222,7 +226,10 @@ begin
end if;
-- Output quad register
if counter(11) = '0' then
if version = '0' then
quad <= VERSION_NUM;
psync <= '0';
elsif counter(11) = '0' then
if counter(4 downto 0) = "00000" then
quad(11) <= shift_B(3);
quad(10) <= shift_G(3);

11
vhdl/fitting.notes
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@ -230,3 +230,14 @@ FB3 18/18* 29/54 55/90 8/ 9
FB4 13/18 35/54 44/90 7/ 7*
----- ----- ----- -----
66/72 119/216 175/360 29/34
20. Added CPLD version output on Quad()
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 31/54 45/90 5/ 9
FB2 17/18 26/54 35/90 9/ 9*
FB3 18/18* 30/54 61/90 9/ 9*
FB4 13/18 36/54 47/90 7/ 7*
----- ----- ----- -----
66/72 123/216 188/360 30/34

15
vhdl_alt/RGBtoHDMI.vhdl
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@ -6,7 +6,7 @@
-- Project Name: RGBtoHDMI
-- Target Devices: XC9572XL
--
-- Version: 0.90
-- Version: 0.1
--
----------------------------------------------------------------------------------
library ieee;
@ -38,10 +38,10 @@ entity RGBtoHDMI is
csync: out std_logic;
-- User interface
SW1: in std_logic;
version: in std_logic;
SW1: in std_logic; -- currently unused
SW2: in std_logic; -- currently unused
SW3: in std_logic; -- currently unused
spare: in std_logic; -- currently unused
link: in std_logic; -- currently unused
LED1: out std_logic;
LED2: out std_logic
@ -50,6 +50,10 @@ end RGBtoHDMI;
architecture Behavorial of RGBtoHDMI is
-- Version number: Design_Major_Minor
-- Design: 0 = Normal CPLD, 1 = Alternative CPLD
constant VERSION_NUM : std_logic_vector(11 downto 0) := x"101";
-- For Modes 0..6
constant default_offset : unsigned(11 downto 0) := to_unsigned(4096 - 64 * 17 + 6, 12);
@ -255,7 +259,10 @@ begin
end if;
-- Output quad register
if counter(11) = '0' then
if version = '0' then
quad <= VERSION_NUM;
psync <= '0';
elsif counter(11) = '0' then
if counter(4 downto 0) = "00001" then
quad(11) <= shift_B(3);
quad(10) <= shift_G(3);

11
vhdl_alt/fitting.notes
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@ -246,3 +246,14 @@ FB3 18/18* 30/54 50/90 9/ 9*
FB4 18/18* 42/54 66/90 6/ 7
----- ----- ----- -----
71/72 132/216 196/360 27/34
20. Added CPLD version output on Quad()
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 33/54 45/90 5/ 9
FB2 17/18 26/54 36/90 8/ 9
FB3 18/18* 30/54 58/90 9/ 9*
FB4 18/18* 47/54 70/90 6/ 7
----- ----- ----- -----
71/72 136/216 209/360 28/34