VHDL: formatting only, remove tabs

Change-Id: I3123b5ab7751c95953b5b5dd889c50c120324b95

vhdl/RGBtoHDMI.vhdl

@@ -26,7 +26,7 @@ entity RGBtoHDMI is
         G1_I:      in    std_logic;
         B1:        in    std_logic;
         csync_in:  in    std_logic;
-		  vsync_in:  in    std_logic;
+        vsync_in:  in    std_logic;
         analog:    inout std_logic;
 
         -- From Pi
@@ -69,7 +69,7 @@ architecture Behavorial of RGBtoHDMI is
 
     -- Sampling points
     constant INIT_SAMPLING_POINTS : std_logic_vector(23 downto 0) := "000000011011011011011011";
-	 
+
     signal shift_R  : std_logic_vector(3 downto 0);
     signal shift_G  : std_logic_vector(3 downto 0);
     signal shift_B  : std_logic_vector(3 downto 0);
@@ -132,32 +132,32 @@ architecture Behavorial of RGBtoHDMI is
     signal toggle   : std_logic;
 
     -- RGB Input Mux
-	 signal old_mux  : std_logic;
+    signal old_mux  : std_logic;
     signal R        : std_logic;
     signal G        : std_logic;
     signal B        : std_logic;
 
-	 signal new_mux  : std_logic;    
-	 signal G0       : std_logic;
+    signal new_mux  : std_logic;
+    signal G0       : std_logic;
     signal G1       : std_logic;
 
-	 signal clamp_int    : std_logic;    
-	 signal clamp_enable : std_logic;
+    signal clamp_int    : std_logic;
+    signal clamp_enable : std_logic;
     signal swap_bits    : std_logic;
 
 begin
-	 old_mux <= mux when not(SupportAnalog) else '0';
+    old_mux <= mux when not(SupportAnalog) else '0';
     R <= R1   when old_mux = '1' else R0;
     G <= G1_I when old_mux = '1' else G0_I;
     B <= B1   when old_mux = '1' else B0;
-	 
-    new_mux <= mux when SupportAnalog else '0';	 
-	 clamp_enable <= '1' when new_mux = '1' else version;
+
+    new_mux <= mux when SupportAnalog else '0';
+    clamp_enable <= '1' when new_mux = '1' else version;
     swap_bits <= vsync_in when new_mux = '1' else '0';
 
-	 G0 <= G1_I when swap_bits = '1' else G0_I;
-	 G1 <= G0_I when swap_bits = '1' else G1_I;
-	 
+    G0 <= G1_I when swap_bits = '1' else G0_I;
+    G1 <= G0_I when swap_bits = '1' else G1_I;
+
     offset_A <= sp_reg(2 downto 0);
     offset_B <= sp_reg(5 downto 3);
     offset_C <= sp_reg(8 downto 6);
@@ -200,10 +200,10 @@ begin
                 if csync_counter = 3 then
                     csync2 <= csync1;
                 end if;
-            end if;	 
-				
-				-- Counter is used to find sampling point for first pixel            
-				last <= csync2;
+            end if;
+
+            -- Counter is used to find sampling point for first pixel
+            last <= csync2;
             -- reset counter on the rising edge of csync
             if last = '0' and csync2 = '1' then
                 if rate(1) = '1' then
@@ -368,13 +368,13 @@ begin
                     psync <= counter(6); -- subsample
                 end if;
             end if;
-			
+
         end if;
     end process;
-	 
-    csync <= csync2; -- output the registered version to save a macro-cell    
-	 
-	 clamp_int <= not(csync1 or csync2);   -- csync2 is cleaned but delayed so OR with csync1 to remove delay on trailing edge of sync pulse
+
+    csync <= csync2; -- output the registered version to save a macro-cell
+
+    clamp_int <= not(csync1 or csync2);   -- csync2 is cleaned but delayed so OR with csync1 to remove delay on trailing edge of sync pulse
 
     analog <= 'Z' when clamp_enable = '0' else clamp_int;
 

vhdl_YUV_6bit/RGBtoHDMI.vhdl

@@ -25,7 +25,7 @@ entity RGBtoHDMI is
         HS_I:      in    std_logic;
         FS_I:      in    std_logic;
 
-		  -- To Atom L/PA/PB Comparators
+        -- To Atom L/PA/PB Comparators
         clamp:     out   std_logic;
 
         -- From Pi
@@ -33,7 +33,7 @@ entity RGBtoHDMI is
         sp_clk:    in    std_logic;
         sp_clken:  in    std_logic;
         sp_data:   in    std_logic;
-		  mux:       in    std_logic;
+        mux:       in    std_logic;
 
         -- To PI GPIO
         quad:      out   std_logic_vector(11 downto 0);
@@ -69,7 +69,7 @@ architecture Behavorial of RGBtoHDMI is
     signal shift_rl : std_logic_vector(1 downto 0);
     signal shift_gl : std_logic_vector(1 downto 0);
     signal shift_bl : std_logic_vector(1 downto 0);
-	 
+
     -- The sampling counter runs at 8x pixel clock of 7.15909MHz = 56.272720MHz
     --
     -- The luminance signal is sampled every  8 counts (bits 2..0)
@@ -89,7 +89,7 @@ architecture Behavorial of RGBtoHDMI is
     signal offset   : unsigned (3 downto 0);
     signal filter_C : std_logic;
     signal filter_L : std_logic;
-	 signal invert   : std_logic;
+    signal invert   : std_logic;
 
     -- Sample pixel on next clock; pipelined to reduce the number of product terms
     signal sample_C : std_logic;
@@ -126,22 +126,22 @@ architecture Behavorial of RGBtoHDMI is
 
     signal HS1      : std_logic;
     signal HS2      : std_logic;
-    signal FS1      : std_logic;	
-	 
+    signal FS1      : std_logic;
+
     signal LL_S      : std_logic;
     signal LH_S      : std_logic;
     signal swap_bits : std_logic;
-	 
+
 begin
     offset <= unsigned(sp_reg(3 downto 0));
     filter_C <= sp_reg(4);
     filter_L <= sp_reg(5);
-	 invert <= sp_reg(6);
-	 
+    invert <= sp_reg(6);
+
     swap_bits <= FS_I when mux = '1' else '0';
 
-	 LL_S <= LH_I when swap_bits = '1' else LL_I;
-	 LH_S <= LL_I when swap_bits = '1' else LH_I;
+    LL_S <= LH_I when swap_bits = '1' else LL_I;
+    LH_S <= LL_I when swap_bits = '1' else LH_I;
 
     -- Shift the bits in LSB first
     process(sp_clk)
@@ -200,8 +200,8 @@ begin
             BL3 <= BL2;
             BH3 <= BH2;
 
-				LL1 <= LL_S;
-				LH1 <= LH_S;
+            LL1 <= LL_S;
+            LH1 <= LH_S;
 
             LL2 <= LL1;
             LL3 <= LL2;