David Banks
|
cb5a8461b6
|
CPLD: Start sampling 8us earlier
Change-Id: I0f1215f801f46472597130476e8912a25bf00e38
|
2018-11-11 17:20:58 +00:00 |
David Banks
|
035381c1fc
|
CPLD: Increment to version 2.0 and update checked-in .jed file
Change-Id: I58fe111c1bf969abe7692cffacd7d20a73647df6
|
2018-10-29 15:27:31 +00:00 |
David Banks
|
8658dfc9cc
|
CPLD: Make bits 7..4 of the MODE 7 offset counter programmable
Change-Id: Icc44f2b90d27548559283236f8a7df749d817d4b
|
2018-10-29 15:26:16 +00:00 |
David Banks
|
5d7839ec84
|
CPLD: Re-centred MODE 7 screen
Change-Id: I70d8d27c773cddb849985c7ead85a71faaf8ed8b
|
2018-10-25 11:01:36 +01:00 |
David Banks
|
a546d6bd42
|
CPLD: Updated released .jed file to v1.1
Change-Id: I2bdeddc68e3e3606425bae5d779a8db7729a8dac
|
2018-10-16 15:53:52 +01:00 |
David Banks
|
7369f6416f
|
CPLD: Reduce csync de-glitch counter to 2 bits
Change-Id: I5752c6f15cc8c69a656187a9c94d5172df276586
|
2018-10-15 21:58:42 +01:00 |
David Banks
|
a91f915022
|
CPLD: De-glitch both states of csync
Change-Id: Id0ad7dca9ab36fc39bef246896c2f4fcc9a34cc1
|
2018-10-15 20:53:12 +01:00 |
David Banks
|
4c9a79cc01
|
CPLD: increased de-glitching (IanB's issue) but still unresolved
Change-Id: I255bdba7d2b42d5078b3e4d616c3b1deee9ca466
|
2018-10-15 16:19:23 +01:00 |
David Banks
|
54bba7c5e1
|
Added JEDEC file for the 1.0 release
Change-Id: I78e6c0897c3825954e9a9a5ec4b9b676323d24eb
|
2018-09-23 12:38:00 +01:00 |
David Banks
|
b2ed64acee
|
CPLD: Start counting off leading edge of HSYNC
Change-Id: I3c1baa29f3db2183ce6920870bcb4e7c936c1b6b
|
2018-07-15 15:36:02 +01:00 |
David Banks
|
6982b3149a
|
CPLD: Corrected sampling offset to better centre screen; CPLD version now 0.9
Change-Id: I2ef25e2bda982080329deaf6569299c695d7ee1d
|
2018-07-15 15:31:51 +01:00 |
David Banks
|
fc342ad0b0
|
Normal CPLD: de-glitch csync (needs to be low for 3 samples)
Change-Id: I6d071cdd003536bc13dfa7fd24ede67a1a25d56c
|
2018-06-22 11:45:05 +01:00 |
David Banks
|
ae88d35ce7
|
CPLD: final pinout changes
Change-Id: I8b18f9f4b3445a79b82b5667971725cb8636fe9a
|
2018-06-12 12:39:06 +01:00 |
David Banks
|
d49c1896fb
|
CPLD: Juggled GPIO assignments so CPLD pin 33 (GSR) connects to GPIO18 (Version)
Change-Id: I6ea4e6ad40d7eb4f785df31ae14a446e05a0be46
|
2018-06-12 10:22:29 +01:00 |
David Banks
|
5383f60c29
|
CPLD: Added configurable half-pixel delay
Change-Id: I98a708d4e6dd753198e8db7d4c03447a61557648
|
2018-06-09 20:41:06 +01:00 |
David Banks
|
c595278204
|
CPLD: Added version support to both CPLDs
Change-Id: Ie2b0698a4ba523b392507349a37a6554daafbc0b
|
2018-06-09 13:24:47 +01:00 |
David Banks
|
9dd59b9990
|
CPLD Normal: Dropped sp_default and made more similar to alternative
Change-Id: Idd72c5478b49bd2977b49b8a3640ed243c259ac9
|
2018-06-09 11:34:04 +01:00 |
David Banks
|
7396747665
|
CPLD and Pi Firmware: Revert to Quad starting at GPIO2
Change-Id: I1a9eeb28150b83e2183c516643d7d65330783697
|
2018-06-09 11:32:03 +01:00 |
David Banks
|
9f37dafa12
|
CPLD: Added global buffer for sp_clk
Change-Id: Id572c9e95d166311e7d46512da9fa45a05c1131d
|
2018-06-08 20:39:29 +01:00 |
David Banks
|
5cf77dc03c
|
CPLD: Updated pinout to quad starts at gpio0, sp_clken now a global input
Change-Id: Ie8ed78de07dce868f644041806361f73b575a403
|
2018-06-08 07:35:27 +01:00 |
David Banks
|
33267363fa
|
CPLD: Load always in cycle 0
Change-Id: I608232e173c99b7006d4dc76d5b235f714103fe8
|
2018-06-07 17:39:18 +01:00 |
David Banks
|
c7f706b4ef
|
CPLD: Update counter to hopefully implement more efficiently
Change-Id: I527318936fce0d83f3f3723a5e68838eb3013f68
|
2018-06-07 17:35:51 +01:00 |
David Banks
|
87eb7535d6
|
CPLD: Mostly cosmetic seperation of the logic into several blocks
Change-Id: Ifacf6b9ad74eead8a4f0f48d59335d28fb1f9740
|
2018-06-07 17:14:02 +01:00 |
David Banks
|
645fc94373
|
CPLD: replace counter2 with load, saving two macro blocks
Change-Id: I67c6a08b7526ef4a35998e93e537693a1e4d78ad
|
2018-06-07 12:53:25 +01:00 |
David Banks
|
ba112a6aad
|
CPLD: Added spare (gpio0) and sp_clken (gpio1)
Change-Id: I74b1af2fe1b51e5e15645b8758ea2a9952649c2c
|
2018-06-06 17:51:11 +01:00 |
David Banks
|
aa10d4273a
|
CPLD: removed a tmp file accidentally checked in
Change-Id: I4dc2fab5b7ec1818a3d058363610abb8ec2f4699
|
2018-06-06 14:51:51 +01:00 |
David Banks
|
847e8db731
|
CPLD: removed SW1 from sp_ref assignment block (prone to noise on prototype)
Change-Id: I053e5019795511410b3474209bf7cf2f4a4de1ee
|
2018-06-06 14:48:51 +01:00 |
David Banks
|
a92cb3d43f
|
CPLD and Pi Firmware: swapped gpio assignments for gpio20 and gpio23 (sp_clk and sp_data) as prototype had noise spikes on gpio20
Change-Id: Ibb2dc20c738e499dc106d61fec516b8fc35bdf73
|
2018-06-06 14:39:02 +01:00 |
David Banks
|
76e055d293
|
CPLD: Removed SW1Out passthrough to save a product term
Change-Id: Ib22720e83a89e11233093768de3c1f4ca5b60017
|
2018-06-06 14:28:12 +01:00 |
David Banks
|
88a183e3ee
|
KiCad and CPLD: final small changes to bring SW2/3/link inputs and LED1 output to CPLD (unused)
Change-Id: I054dcab88885547d6ceb07bc2759daf81372ef52
|
2018-06-05 18:58:11 +01:00 |
David Banks
|
65b90f2ba4
|
CPLD: Updated to pinout from PCB based design
Change-Id: Ia13272589b9886c587bef7645dd2ee0809ac1e7f
|
2018-06-05 17:52:51 +01:00 |
David Banks
|
2dc99dccaa
|
Added support for manual calibration button
Change-Id: I00867668c208bea174b88650ac8fc25d7767c3ed
|
2017-05-28 12:09:58 +01:00 |
David Banks
|
e7675e9fa8
|
Fix counter pipelining issue
Change-Id: I66584fbf2dfb375dd7e77b5f4a214224b2552519
|
2017-05-25 19:31:43 +01:00 |
David Banks
|
082f772e55
|
Moved to 6 sampling points in Mode 7
Change-Id: I888d9911fe6be96f48bf9429650b4a13ae3c185d
|
2017-05-25 17:23:49 +01:00 |
David Banks
|
81720e677c
|
Route SW through CPLD to Pi
Change-Id: I467e7a5b4df797d0770dce132d007cfe2c63234f
|
2017-05-25 15:12:09 +01:00 |
David Banks
|
97394525a6
|
Auto-calibration: work in progress
Change-Id: I4311e1dcd6e290c0d4e74d9552a75862426bdccf
|
2017-05-25 08:40:49 +01:00 |
David Banks
|
70d559303d
|
Make sampling points soft-programmable by the Pi
Change-Id: I42a1a73e084779106953d019809e4be943c76ead
|
2017-05-24 13:20:06 +01:00 |
David Banks
|
009db18ad7
|
Use a 96MHz clock in both modes
Change-Id: If47c36cb655a638c6997464af40ed4874da6766f
|
2017-05-23 13:03:27 +01:00 |
David Banks
|
c169996467
|
Calibrate clock based on VSYNC time
Change-Id: I39dab208f2af217662921ffca6f5f8f69c7d6edb
|
2017-04-27 15:27:26 +01:00 |
David Banks
|
00e555bfdf
|
Automatic mode 7 support
Change-Id: I93568cd3822e7e5aed9ff8b61d62eaa8a4fda193
|
2017-04-26 22:19:41 +01:00 |
David Banks
|
6d0263f280
|
Removed obsolete VSYNC logic from CPLD, pass through CSYNC to ARM
Change-Id: I01c855dfd71e225bafbc5a03841581e9ff5c33cb
|
2017-04-26 18:15:47 +01:00 |
David Banks
|
4335d4e531
|
Early work on Mode 7
Change-Id: I0cea302fd7ea9ea8cb3649721185c2351b7084dc
|
2017-04-25 18:24:49 +01:00 |
David Banks
|
a0b2817ab1
|
Tweak sampling position by one notch
Change-Id: I4dfdb5c424b584596b2beabb5df0e86e4ba393eb
|
2017-04-25 12:55:47 +01:00 |
David Banks
|
123ae936e1
|
Set all outputs to SLOW to reduce noise
Change-Id: I8d28858c0972310a24c561575e341613278cfaa7
|
2017-04-25 12:55:20 +01:00 |
David Banks
|
cf17594877
|
Implemented vsync
Change-Id: I35d7dc7a0184e147faa64fadf038752e7df467b9
|
2017-04-25 11:53:22 +01:00 |
David Banks
|
29d99e7110
|
VHDL: Adjust count when quad loaded
Change-Id: Ieaf096aa6ffb574e470564ca70602ee92bde57ce
|
2017-04-25 10:06:38 +01:00 |
David Banks
|
6c519cdc29
|
VHDL: idle psync should be zero
Change-Id: I3422fb75376be0c3a29e8f02b5019910e9c84614
|
2017-04-25 09:57:21 +01:00 |
David Banks
|
140b89d311
|
VHDL: Increased counter to 11 bits
Change-Id: I269a63881ae52115f5989f72e85a536ed79f7e2f
|
2017-04-25 09:53:15 +01:00 |
David Banks
|
e3dbea5b30
|
VHDL: Updated .xise file
Change-Id: I8d8fdbac96ed32383779f61b69c88800ee6bfcf9
|
2017-04-25 09:52:49 +01:00 |
David Banks
|
7fa14552bd
|
Initial version of VHDL
Change-Id: I2fbdf73bc0feb8955a2b4b70856203e370cbad30
|
2017-04-24 20:21:18 +01:00 |