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CPLD: Added spare (gpio0) and sp_clken (gpio1) 

Change-Id: I74b1af2fe1b51e5e15645b8758ea2a9952649c2c
dev2
David Banks 2018-06-06 17:51:11 +01:00
rodzic cf0b760c86
commit ba112a6aad
3 zmienionych plików z 23 dodań i 6 usunięć
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10
vhdl/RGBtoHDMI.ucf
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@ -19,24 +19,26 @@ NET "SW1" LOC = "P39"; # input gpio16
NET "SW2" LOC = "P40"; # input gpio26
NET "SW3" LOC = "P41"; # input gpio19
NET "link" LOC = "P42"; # input gpio25 (connects to link / test point)
NET "spare" LOC = "P7"; # input gpio0
NET "mode7" LOC = "P19"; # input gpio22
NET "elk" LOC = "P18"; # input gpio24
NET "sp_data" LOC = "P44"; # input gpio20
NET "sp_clk" LOC = "P20"; # input gpio23
NET "sp_clken" LOC = "P6"; # input gpio1
NET "quad(0)" LOC = "P29"; # output gpio2
NET "quad(1)" LOC = "P28"; # output gpio3
NET "quad(2)" LOC = "P27"; # output gpio4
NET "quad(3)" LOC = "P7"; # output gpio5
NET "quad(4)" LOC = "P5"; # output gpio6
NET "quad(3)" LOC = "P5"; # output gpio5
NET "quad(4)" LOC = "P2"; # output gpio6
NET "quad(5)" LOC = "P8"; # output gpio7
NET "quad(6)" LOC = "P12"; # output gpio8
NET "quad(7)" LOC = "P14"; # output gpio9
NET "quad(8)" LOC = "P16"; # output gpio10
NET "quad(9)" LOC = "P13"; # output gpio11
NET "quad(10)" LOC = "P6"; # output gpio12
NET "quad(11)" LOC = "P3"; # output gpio13
NET "quad(10)" LOC = "P3"; # output gpio12
NET "quad(11)" LOC = "P1"; # output gpio13
NET "psync" LOC = "P22"; # output gpio17
NET "csync" LOC = "P23"; # output gpio18

8
vhdl/RGBtoHDMI.vhdl
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@ -29,6 +29,7 @@ entity RGBtoHDMI is
mode7: in std_logic;
elk: in std_logic;
sp_clk: in std_logic;
sp_clken: in std_logic;
sp_data: in std_logic;
-- To PI GPIO
@ -37,10 +38,11 @@ entity RGBtoHDMI is
csync: out std_logic;
-- User interface
link: in std_logic; -- currently unused
SW1: in std_logic;
SW2: in std_logic; -- currently unused
SW3: in std_logic; -- currently unused
spare: in std_logic; -- currently unused
link: in std_logic; -- currently unused
LED1: out std_logic;
LED2: out std_logic
);
@ -127,7 +129,9 @@ begin
--if SW1 = '0' then
-- sp_reg <= INIT_SAMPLING_POINTS;
if rising_edge(sp_clk) then
sp_reg <= sp_data & sp_reg(sp_reg'left downto sp_reg'right + 1);
if sp_clken = '1' then
sp_reg <= sp_data & sp_reg(sp_reg'left downto sp_reg'right + 1);
end if;
end if;
end process;

11
vhdl/fitting.notes
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@ -164,3 +164,14 @@ FB3 18/18* 37/54 61/90 9/ 9*
FB4 18/18* 39/54 58/90 7/ 7*
----- ----- ----- -----
72/72 135/216 219/360 28/34
14. Added sp_clken and spare
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 30/54 63/90 5/ 9
FB2 18/18* 26/54 46/90 9/ 9*
FB3 18/18* 35/54 60/90 8/ 9
FB4 18/18* 47/54 71/90 7/ 7*
----- ----- ----- -----
72/72 138/216 240/360 29/34