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CPLD and Pi Firmware: Revert to Quad starting at GPIO2 

Change-Id: I1a9eeb28150b83e2183c516643d7d65330783697
issue_1022
David Banks 2018-06-09 10:06:00 +01:00
rodzic 90e8b0c045
commit 7396747665
3 zmienionych plików z 34 dodań i 34 usunięć
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8
src/defs.h
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@ -113,8 +113,8 @@
#endif // __ASSEMBLER__
// Quad Pixel input on GPIOs 0..11
#define PIXEL_BASE (0)
// Quad Pixel input on GPIOs 2..13
#define PIXEL_BASE (2)
#define SW1_PIN (16) // active low
#define SW2_PIN (26) // active low
@ -124,11 +124,11 @@
#define MODE7_PIN (22)
#define GPCLK_PIN (21)
#define SP_CLK_PIN (20)
#define SP_CLKEN_PIN (13)
#define SP_CLKEN_PIN (1)
#define SP_DATA_PIN (23)
#define MUX_PIN (24)
#define LINK_PIN (25)
#define SPARE_PIN (12)
#define SPARE_PIN (0)
// LED1 is left LED, driven by the Pi
// LED2 is the right LED, driven by the CPLD, as a copy of mode 7

32
src/rgb_to_fb.S
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@ -235,42 +235,42 @@ process_chars_loop:
// Wait for 0-1 edge on PSYNC
WAIT_FOR_PSYNC_1
// Pixel 0 in GPIO 2..0 -> 7.. 4
// Pixel 1 in GPIO 5..3 -> 3.. 0
// Pixel 2 in GPIO 8..6 -> 15..12
// Pixel 3 in GPIO 11..9 -> 11.. 8
// Pixel 0 in GPIO 4.. 2 -> 7.. 4
// Pixel 1 in GPIO 7.. 5 -> 3.. 0
// Pixel 2 in GPIO 10.. 8 -> 15..12
// Pixel 3 in GPIO 13..11 -> 11.. 8
and r9, r8, #(7 << PIXEL_BASE)
orr r10, r10, r9, lsl #4
orr r10, r10, r9, lsl #(4 - PIXEL_BASE)
and r9, r8, #(7 << (PIXEL_BASE + 3))
orr r10, r10, r9, lsr #3
orr r10, r10, r9, lsr #(3 + PIXEL_BASE)
and r9, r8, #(7 << (PIXEL_BASE + 6))
orr r10, r10, r9, lsl #6
orr r10, r10, r9, lsl #(6 - PIXEL_BASE)
and r9, r8, #(7 << (PIXEL_BASE + 9))
orr r10, r10, r9, lsr #1
orr r10, r10, r9, lsr #(1 + PIXEL_BASE)
// Wait for 1-0 edge on PSYNC
WAIT_FOR_PSYNC_0
// Pixel 4 in GPIO 2..0 -> 23..20
// Pixel 5 in GPIO 5..3 -> 19..16
// Pixel 6 in GPIO 8..6 -> 31..28
// Pixel 7 in GPIO 11..9 -> 27..24
// Pixel 4 in GPIO 4.. 2 -> 23..20
// Pixel 5 in GPIO 7.. 5 -> 19..16
// Pixel 6 in GPIO 10.. 8 -> 31..28
// Pixel 7 in GPIO 13..11 -> 27..24
and r9, r8, #(7 << PIXEL_BASE)
orr r10, r10, r9, lsl #20
orr r10, r10, r9, lsl #(20 - PIXEL_BASE)
and r9, r8, #(7 << (PIXEL_BASE + 3))
orr r10, r10, r9, lsl #13
orr r10, r10, r9, lsl #(13 - PIXEL_BASE)
and r9, r8, #(7 << (PIXEL_BASE + 6))
orr r10, r10, r9, lsl #22
orr r10, r10, r9, lsl #(22 - PIXEL_BASE)
and r9, r8, #(7 << (PIXEL_BASE + 9))
orr r10, r10, r9, lsl #15
orr r10, r10, r9, lsl #(15 - PIXEL_BASE)
// Line double always in Modes 0-6 regardless of interlace
// On the multi core Pi this introduces stalling artefacts

28
vhdl/RGBtoHDMI.ucf
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@ -26,26 +26,26 @@ NET "SW1" LOC = "P39"; # input gpio16
NET "SW2" LOC = "P40"; # input gpio26
NET "SW3" LOC = "P41"; # input gpio19
NET "link" LOC = "P42"; # input gpio25 (connects to link / test point)
NET "spare" LOC = "P3"; # input gpio12
NET "spare" LOC = "P7"; # input gpio0
NET "mode7" LOC = "P19"; # input gpio22
NET "elk" LOC = "P18"; # input gpio24
NET "sp_clk" LOC = "P44"; # input gpio20
NET "sp_data" LOC = "P20"; # input gpio23
NET "sp_clken" LOC = "P1"; # input gpio13
NET "sp_clken" LOC = "P6"; # input gpio1
NET "quad(0)" LOC = "P7"; # output gpio0
NET "quad(1)" LOC = "P6"; # output gpio1
NET "quad(2)" LOC = "P29"; # output gpio2
NET "quad(3)" LOC = "P28"; # output gpio3
NET "quad(4)" LOC = "P27"; # output gpio4
NET "quad(5)" LOC = "P5"; # output gpio5
NET "quad(6)" LOC = "P2"; # output gpio6
NET "quad(7)" LOC = "P8"; # output gpio7
NET "quad(8)" LOC = "P12"; # output gpio8
NET "quad(9)" LOC = "P14"; # output gpio9
NET "quad(10)" LOC = "P16"; # output gpio10
NET "quad(11)" LOC = "P13"; # output gpio11
NET "quad(0)" LOC = "P29"; # output gpio2
NET "quad(1)" LOC = "P28"; # output gpio3
NET "quad(2)" LOC = "P27"; # output gpio4
NET "quad(3)" LOC = "P5"; # output gpio5
NET "quad(4)" LOC = "P2"; # output gpio6
NET "quad(5)" LOC = "P8"; # output gpio7
NET "quad(6)" LOC = "P12"; # output gpio8
NET "quad(7)" LOC = "P14"; # output gpio9
NET "quad(8)" LOC = "P16"; # output gpio10
NET "quad(9)" LOC = "P13"; # output gpio11
NET "quad(10)" LOC = "P3"; # output gpio12
NET "quad(11)" LOC = "P1"; # output gpio13
NET "psync" LOC = "P22"; # output gpio17
NET "csync" LOC = "P23"; # output gpio18