kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
David Banks
rodzic
29d99e7110
commit
cf17594877
113
src/rgb_to_fb.S
113
src/rgb_to_fb.S
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@ -1,33 +1,68 @@
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#include "rpi-base.h"
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#include "defs.h"
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.text
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.global rgb_to_fb
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// r0 = pointer to frame buffer
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// r1
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// r2
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// r3
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// r3 = field offset
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// r4 = GPLEV0
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// r5 = line counter
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// r6 = pixel counter
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// r8 = value read from GPLEV0
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// r9 = extracted pixel
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// r10 = block of 8 pixels, to be written to FB
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// r10 = block of 8 pixels, to be written to FB
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rgb_to_fb:
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push {r4-r12, lr}
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push {r4-r12, lr}
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mov r3, #0
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ldr r4, =GPLEV0
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frame:
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// Update field offset to alternate field
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eor r3, r3, #320
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// Set framebuffer address
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add r1, r0, r3
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// Wait for start of vsync
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wait_for_vsync_a:
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ldr r8, [r4]
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tst r8, #VSYNC_MASK
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beq wait_for_vsync_a
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// Wait for end of vsync
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wait_for_vsync_b:
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ldr r8, [r4]
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tst r8, #VSYNC_MASK
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bne wait_for_vsync_b
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// Skip inactive lines
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mov r5, #28
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loop0:
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mov r1, r0
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ldr r4, =GPLEV0
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mov r5, #256
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loop1:
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wait_for_hsync_a:
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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beq wait_for_hsync_a
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wait_for_hsync_b:
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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bne wait_for_hsync_b
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subs r5, r5, #1
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bne loop0
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// Process active lines
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mov r5, #256
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loop1:
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// Wait for active high hsync
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wait_for_hsync:
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ldr r8, [r4]
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@ -40,7 +75,7 @@ loop2:
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// Initialize 8 pixel block
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mov r10, #0
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// Wait for 0-1 edge on PSYNC
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wait_psync_01:
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ldr r8, [r4]
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@ -51,10 +86,10 @@ wait_psync_01:
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// Pixel 1 in GPIO 7.. 5 -> 3.. 0
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// Pixel 2 in GPIO 10.. 8 -> 15..12
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// Pixel 3 in GPIO 13..11 -> 11.. 8
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and r9, r8, #(7 << PIXEL_BASE)
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orr r10, r10, r9, lsl #2
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and r9, r8, #(7 << (PIXEL_BASE + 3))
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orr r10, r10, r9, lsr #5
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@ -74,10 +109,10 @@ wait_psync_10:
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// Pixel 5 in GPIO 7.. 5 -> 19..16
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// Pixel 6 in GPIO 10.. 8 -> 31..28
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// Pixel 7 in GPIO 13..11 -> 27..24
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and r9, r8, #(7 << PIXEL_BASE)
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orr r10, r10, r9, lsl #18
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and r9, r8, #(7 << (PIXEL_BASE + 3))
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orr r10, r10, r9, lsl #11
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@ -87,43 +122,21 @@ wait_psync_10:
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and r9, r8, #(7 << (PIXEL_BASE + 9))
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orr r10, r10, r9, lsl #13
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str r10, [r1], #4
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subs r6, r6, #1
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bne loop2
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// Skip a whole line
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subs r6, r6, #1
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bne loop2
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// Skip a whole line to maintain aspect ratio
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add r1, r1, #320
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subs r5, r5, #1
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bne loop1
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subs r5, r5, #1
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bne loop1
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b frame
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// Temporary hack - skip inactive lines
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ldr r5, =(312-256)
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loop3:
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wait_for_hsync_a:
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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beq wait_for_hsync_a
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// Return
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wait_for_hsync_b:
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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bne wait_for_hsync_b
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pop {r4-r12, lr}
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mov pc, lr
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subs r5, r5, #1
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bne loop3
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b loop0
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// Return
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pop {r4-r12, lr}
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mov pc, lr
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@ -43,6 +43,7 @@ architecture Behavorial of RGBtoHDMI is
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signal shift : std_logic_vector(11 downto 0);
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signal nCSYNC1 : std_logic;
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signal nCSYNC2 : std_logic;
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-- The counter runs at 4x pixel clock
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--
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@ -80,15 +81,40 @@ begin
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if rising_edge(clk) then
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-- synchronize nCSYNC to the sampling clock
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nCSYNC1 <= nCSYNC;
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nCSYNC2 <= nCSYNC1;
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if nCSYNC1 = '0' then
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-- within horizontal line sync pulse
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if nCSYNC1 = '0' and nCSYNC2 = '1' then
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-- start of horizontal line sync pulse
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hsync <= '1';
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psync <= '0';
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-- counter is used to measure how long the pulse is
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counter <= to_unsigned(0, counter'length);
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elsif nCSYNC1 = '1' and nCSYNC2 = '0' then
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-- end of horizontal line sync pulse
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hsync <= '0';
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-- test for vertical sync
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-- a normal line sync pulse is 4us
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-- a saturated counter (512 == 8us) value can only happen during vsync
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if counter = 512 then
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vsync <= '1';
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else
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vsync <= '0';
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end if;
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-- counter is used to find sampling point for first pixel
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counter <= to_unsigned(1311, counter'length);
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elsif nCSYNC1 = '0' then
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-- within the line sync pulse
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-- saturate counter at 8us.
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if counter < 512 then
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counter <= counter + 1;
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end if;
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else
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-- within the line
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hsync <= '0';
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if counter = 31 then
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counter <= to_unsigned(0, counter'length);
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else
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@ -110,6 +136,8 @@ begin
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end if;
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end process;
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field <= '1';
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LED1 <= not SW;
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LED2 <= led_counter(led_counter'left);
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