23 Commity (15d1a71e0cc2c4bff11f18e6daf6bdaa6e2514d4)

Autor	SHA1	Wiadomość	Data
IanSB	9076eb238b	Update common VHDL with support for new RGB/YUV board (RGB7.1 / YUV3.1)	2019-12-17 02:35:04 +00:00
David Banks	98170366a5	Refactor xilinx projects so vhdl_bbc and vhdl_RGB_6bit share same vhdl/ucf file ... Change-Id: I7c6db57f6b1fe8331dbeaacc81e49e8239349625	2019-12-05 14:34:59 +00:00
IanSB	c3d1ac43de	Update CPLD to v6.5: Add new mux option in 6 bit mode using the Vsync input for monochrome video	2019-11-10 02:30:51 +00:00
David Banks	ae88d35ce7	CPLD: final pinout changes ... Change-Id: I8b18f9f4b3445a79b82b5667971725cb8636fe9a	2018-06-12 12:39:06 +01:00
David Banks	d49c1896fb	CPLD: Juggled GPIO assignments so CPLD pin 33 (GSR) connects to GPIO18 (Version) ... Change-Id: I6ea4e6ad40d7eb4f785df31ae14a446e05a0be46	2018-06-12 10:22:29 +01:00
David Banks	c595278204	CPLD: Added version support to both CPLDs ... Change-Id: Ie2b0698a4ba523b392507349a37a6554daafbc0b	2018-06-09 13:24:47 +01:00
David Banks	7396747665	CPLD and Pi Firmware: Revert to Quad starting at GPIO2 ... Change-Id: I1a9eeb28150b83e2183c516643d7d65330783697	2018-06-09 11:32:03 +01:00
David Banks	9f37dafa12	CPLD: Added global buffer for sp_clk ... Change-Id: Id572c9e95d166311e7d46512da9fa45a05c1131d	2018-06-08 20:39:29 +01:00
David Banks	5cf77dc03c	CPLD: Updated pinout to quad starts at gpio0, sp_clken now a global input ... Change-Id: Ie8ed78de07dce868f644041806361f73b575a403	2018-06-08 07:35:27 +01:00
David Banks	ba112a6aad	CPLD: Added spare (gpio0) and sp_clken (gpio1) ... Change-Id: I74b1af2fe1b51e5e15645b8758ea2a9952649c2c	2018-06-06 17:51:11 +01:00
David Banks	a92cb3d43f	CPLD and Pi Firmware: swapped gpio assignments for gpio20 and gpio23 (sp_clk and sp_data) as prototype had noise spikes on gpio20 ... Change-Id: Ibb2dc20c738e499dc106d61fec516b8fc35bdf73	2018-06-06 14:39:02 +01:00
David Banks	76e055d293	CPLD: Removed SW1Out passthrough to save a product term ... Change-Id: Ib22720e83a89e11233093768de3c1f4ca5b60017	2018-06-06 14:28:12 +01:00
David Banks	88a183e3ee	KiCad and CPLD: final small changes to bring SW2/3/link inputs and LED1 output to CPLD (unused) ... Change-Id: I054dcab88885547d6ceb07bc2759daf81372ef52	2018-06-05 18:58:11 +01:00
David Banks	65b90f2ba4	CPLD: Updated to pinout from PCB based design ... Change-Id: Ia13272589b9886c587bef7645dd2ee0809ac1e7f	2018-06-05 17:52:51 +01:00
David Banks	2dc99dccaa	Added support for manual calibration button ... Change-Id: I00867668c208bea174b88650ac8fc25d7767c3ed	2017-05-28 12:09:58 +01:00
David Banks	e7675e9fa8	Fix counter pipelining issue ... Change-Id: I66584fbf2dfb375dd7e77b5f4a214224b2552519	2017-05-25 19:31:43 +01:00
David Banks	082f772e55	Moved to 6 sampling points in Mode 7 ... Change-Id: I888d9911fe6be96f48bf9429650b4a13ae3c185d	2017-05-25 17:23:49 +01:00
David Banks	81720e677c	Route SW through CPLD to Pi ... Change-Id: I467e7a5b4df797d0770dce132d007cfe2c63234f	2017-05-25 15:12:09 +01:00
David Banks	70d559303d	Make sampling points soft-programmable by the Pi ... Change-Id: I42a1a73e084779106953d019809e4be943c76ead	2017-05-24 13:20:06 +01:00
David Banks	00e555bfdf	Automatic mode 7 support ... Change-Id: I93568cd3822e7e5aed9ff8b61d62eaa8a4fda193	2017-04-26 22:19:41 +01:00
David Banks	6d0263f280	Removed obsolete VSYNC logic from CPLD, pass through CSYNC to ARM ... Change-Id: I01c855dfd71e225bafbc5a03841581e9ff5c33cb	2017-04-26 18:15:47 +01:00
David Banks	123ae936e1	Set all outputs to SLOW to reduce noise ... Change-Id: I8d28858c0972310a24c561575e341613278cfaa7	2017-04-25 12:55:20 +01:00
David Banks	7fa14552bd	Initial version of VHDL ... Change-Id: I2fbdf73bc0feb8955a2b4b70856203e370cbad30	2017-04-24 20:21:18 +01:00