David Banks
|
81720e677c
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Route SW through CPLD to Pi
Change-Id: I467e7a5b4df797d0770dce132d007cfe2c63234f
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2017-05-25 15:12:09 +01:00 |
David Banks
|
392a95a4e5
|
Disable ARM use of L2 cache really helps!
Change-Id: I781daac0866ebe6bad7990161de9e6047aafbbe8
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2017-05-25 13:32:20 +01:00 |
David Banks
|
5f9be9ebda
|
Auto-calibration: work still in progress
Change-Id: I87083aad51929716abbc491eedc619a65396dc95
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2017-05-25 11:12:09 +01:00 |
David Banks
|
97394525a6
|
Auto-calibration: work in progress
Change-Id: I4311e1dcd6e290c0d4e74d9552a75862426bdccf
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2017-05-25 08:40:49 +01:00 |
David Banks
|
70d559303d
|
Make sampling points soft-programmable by the Pi
Change-Id: I42a1a73e084779106953d019809e4be943c76ead
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2017-05-24 13:20:06 +01:00 |
David Banks
|
009db18ad7
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Use a 96MHz clock in both modes
Change-Id: If47c36cb655a638c6997464af40ed4874da6766f
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2017-05-23 13:03:27 +01:00 |
David Banks
|
b85dc03c66
|
Switch over to using the framebuffer interface (channel 1) for initializing the framebuffer
Change-Id: I0b19c2d5071f8295e0adbb2e3b898bfc1232c231
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2017-05-19 09:23:20 +01:00 |
David Banks
|
051a8bc481
|
Dropped PROBE mode as it is now unnecessary, as we can re-initialize the framebuffer multiple times
Change-Id: Ic2942df02241165f60fd71147bf1fb99461f54b3
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2017-05-18 20:18:26 +01:00 |
David Banks
|
1471597d42
|
Switch between 672x540 and 504x540 depending on mode
Change-Id: Iad5ae7f877945400bb7a0947972f7b13d262c3e5
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2017-05-18 19:29:49 +01:00 |
David Banks
|
a30c529ac4
|
Double buffering now working well in all Modes on Pi Zero
Change-Id: I000aa01c2c7b16926f15016446d39cdef2b8e583
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2017-05-02 19:48:17 +01:00 |
David Banks
|
79e23bb3a8
|
Work-in-progress on double buffering - disabled
Change-Id: I4857d087496bbeb8c9368123189052e7876dbb6d
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2017-05-02 14:07:14 +01:00 |
David Banks
|
34a9cafede
|
Workaround for cache stall issues on Pi3
Change-Id: I3213d6f01cb310d697d04eeeb7ca8cf6ac650a34
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2017-05-01 12:42:19 +01:00 |
David Banks
|
2309d11482
|
Custom 1600x1200@50 HDMI mode
Change-Id: Iad27090131dec9bebaee2a865f861cc67a985011
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2017-04-30 19:08:41 +01:00 |
David Banks
|
e5dc79dc37
|
Fixed a bug in clear_screen
Change-Id: I1d77e4d243762b55fb171f4d5b901097ca321183
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2017-04-30 17:12:33 +01:00 |
David Banks
|
9a711f3613
|
Removed some unused Pi3 code
Change-Id: Ia3714459d467b07dc63c7b1a87ee9ce4d2bf3c44
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2017-04-30 17:06:59 +01:00 |
David Banks
|
1763a39b2f
|
Fixes for Pi 3
Change-Id: I1c9d98170b2fb9d0b037f39163fb8a925786bfb5
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2017-04-30 17:02:22 +01:00 |
David Banks
|
88f4fbe38d
|
Comment config.txt
Change-Id: I6281ecd3e68ec3473b271a6897242f394acc1b33
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2017-04-30 15:50:19 +01:00 |
David Banks
|
3d8c7d41e1
|
Tidy up and remove unused code
Change-Id: I8891b771a131bfb1b01596cf9b7d230d6710a20a
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2017-04-30 15:13:57 +01:00 |
David Banks
|
fed6bd5384
|
Updated active area to 672x540 to be more tolerant of *TV settings
Change-Id: If050f2d179673f376e18491acdcdaab2291a9556
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2017-04-30 14:58:36 +01:00 |
David Banks
|
127c804a5e
|
Extended clock calibration to correctly handle 624-line non-interlaced modes
Change-Id: I6aaf957512e0f9d77df89d835f8cf40b4d801506
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2017-04-30 12:55:40 +01:00 |
David Banks
|
4cf99c2a91
|
Overscan horizontally by 32 pixels
Change-Id: Ib4dec873d22a89e4f6463fc0aaa18e7f0952b661
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2017-04-30 12:19:10 +01:00 |
David Banks
|
933728c9d3
|
Only show grey background in DEBUG mode
Change-Id: I96ba90ca3fa9924b28c534af81f9513c5180880b
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2017-04-30 12:18:07 +01:00 |
David Banks
|
5d2c60e23b
|
Improve handling of non-interlaced mode by line doubling
Change-Id: I90ec9457dbf2974b67f666144bf3d11e5bda82bb
|
2017-04-30 11:51:51 +01:00 |
David Banks
|
e0e2d3bfdb
|
Changed some log_info to log_debug
Change-Id: I11d52619675c5bff86fdeb9c4977bd19c5ec7081
|
2017-04-30 10:58:03 +01:00 |
David Banks
|
d54fba890a
|
Made accesses to clock registers volatile
Change-Id: Ieb21bf648ea2c3a52b644a597225a93fd7b32ad8
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2017-04-30 10:57:06 +01:00 |
David Banks
|
8b0cb940f8
|
Deleted unused build files
Change-Id: I3b2a8a327f8509dc2955a2fff038db0266ceaee3
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2017-04-30 10:56:02 +01:00 |
David Banks
|
dac270bc4d
|
Freed up a couple of registers
Change-Id: Ic25ce5edb5dd476db55042711afeed781ec83db5
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2017-04-30 10:42:35 +01:00 |
David Banks
|
6473d100ee
|
Clear screen on entry
Change-Id: Id9eeeb4d12c6daab9f14834eed7c1e145c0150c1
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2017-04-27 21:25:40 +01:00 |
David Banks
|
c169996467
|
Calibrate clock based on VSYNC time
Change-Id: I39dab208f2af217662921ffca6f5f8f69c7d6edb
|
2017-04-27 15:27:26 +01:00 |
David Banks
|
00e555bfdf
|
Automatic mode 7 support
Change-Id: I93568cd3822e7e5aed9ff8b61d62eaa8a4fda193
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2017-04-26 22:19:41 +01:00 |
David Banks
|
6d0263f280
|
Removed obsolete VSYNC logic from CPLD, pass through CSYNC to ARM
Change-Id: I01c855dfd71e225bafbc5a03841581e9ff5c33cb
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2017-04-26 18:15:47 +01:00 |
David Banks
|
1bf8ebb272
|
Switch to software processing of CSYNC to find VSYNC and Odd/Even field
Change-Id: Ied519b072e75da67559f5e867b012c7b5ae74eb1
|
2017-04-26 17:49:23 +01:00 |
David Banks
|
4335d4e531
|
Early work on Mode 7
Change-Id: I0cea302fd7ea9ea8cb3649721185c2351b7084dc
|
2017-04-25 18:24:49 +01:00 |
David Banks
|
b9fc578bff
|
Added a LINE_DOUBLE #define
Change-Id: I0c385d6bca14e9a163ce927927acc34a021635dc
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2017-04-25 15:37:41 +01:00 |
David Banks
|
c9f4d27c1e
|
Set core_freq to 383.9MHz via mailbox
Change-Id: Ic9cc77ecc94bac17e242a9bbab4581a496515086
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2017-04-25 15:14:01 +01:00 |
David Banks
|
2934293d99
|
Improve noise immunity of psync and hsync edge detection - make a big difference!
Change-Id: I4e13402a1f430a20804ed46e4f9d3bb9b9b30860
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2017-04-25 14:48:43 +01:00 |
David Banks
|
a0b2817ab1
|
Tweak sampling position by one notch
Change-Id: I4dfdb5c424b584596b2beabb5df0e86e4ba393eb
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2017-04-25 12:55:47 +01:00 |
David Banks
|
123ae936e1
|
Set all outputs to SLOW to reduce noise
Change-Id: I8d28858c0972310a24c561575e341613278cfaa7
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2017-04-25 12:55:20 +01:00 |
David Banks
|
d11647e620
|
Added some noise immunity to vsync
Change-Id: I7a678fdab841f009742ed2f9857f7d1b83515b45
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2017-04-25 12:05:50 +01:00 |
David Banks
|
cf17594877
|
Implemented vsync
Change-Id: I35d7dc7a0184e147faa64fadf038752e7df467b9
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2017-04-25 11:53:22 +01:00 |
David Banks
|
29d99e7110
|
VHDL: Adjust count when quad loaded
Change-Id: Ieaf096aa6ffb574e470564ca70602ee92bde57ce
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2017-04-25 10:06:38 +01:00 |
David Banks
|
6c519cdc29
|
VHDL: idle psync should be zero
Change-Id: I3422fb75376be0c3a29e8f02b5019910e9c84614
|
2017-04-25 09:57:21 +01:00 |
David Banks
|
140b89d311
|
VHDL: Increased counter to 11 bits
Change-Id: I269a63881ae52115f5989f72e85a536ed79f7e2f
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2017-04-25 09:53:15 +01:00 |
David Banks
|
e3dbea5b30
|
VHDL: Updated .xise file
Change-Id: I8d8fdbac96ed32383779f61b69c88800ee6bfcf9
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2017-04-25 09:52:49 +01:00 |
David Banks
|
27822940d2
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Make virtual frame buffer same size as physical frame buffer
Change-Id: Iba681af707024e891232e455dd7a6575bf4af845
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2017-04-25 09:37:26 +01:00 |
David Banks
|
0ba2591092
|
Switch to 1920x1080
Change-Id: I33c8be2ff723ccf8798eb72ad9193d8c4b383ac1
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2017-04-25 09:35:30 +01:00 |
David Banks
|
84935e5f61
|
Update core clock to 384MHz, add hdmi settings
Change-Id: I6b65f69cab9ed775ba2b0a1363ae2d15cc8b5656
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2017-04-25 07:17:49 +01:00 |
David Banks
|
f4a2b1c8bf
|
Skip alternate lines to maintain aspect ratio
Change-Id: If1112e7b0af8107d88d9709f18e9a9df546a5ea0
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2017-04-25 07:17:07 +01:00 |
David Banks
|
3ab2faf6e4
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Add a grey background to framebuffer for debugging
Change-Id: Ifafe6f724d5294f7920dae5ecda6cbbc03a869ad
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2017-04-25 07:01:39 +01:00 |
David Banks
|
cbb5e4d1b8
|
Fix pixel misordering within byte
Change-Id: I82a20a49b4004dbbb25986a4fce59ea84f197a17
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2017-04-25 07:00:50 +01:00 |