kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Switch to software processing of CSYNC to find VSYNC and Odd/Even field
Change-Id: Ied519b072e75da67559f5e867b012c7b5ae74eb1issue_1022
David Banks
rodzic
4335d4e531
commit
1bf8ebb272
241
src/rgb_to_fb.S
241
src/rgb_to_fb.S
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@ -8,7 +8,7 @@
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// At the moment, this only works with non-interlace
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// video, as there is a bug in the CPLD that introduces
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// line jitter with interlaced video.
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// #define LINE_DOUBLE
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.text
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@ -19,108 +19,183 @@
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// r0 = frame buffer base
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// r1 = 8-pixel characters per line (normally 80, but 62.5 (63) in Mode 7
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// r2 = bytes per line
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// r3 = unused
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//
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// Working registers:
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//
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// r3 = field offsset
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// r4 = GPLEV0
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// r5 = line counter
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// r6 = pixel counter
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// r8 = value read from GPLEV0
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// r9 = extracted pixel
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// r10 = block of 8 pixels, to be written to FB
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// r11 = pointer into frame buffer (start of line)
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// r12 = pointer into frame buffer (moves within line)
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// Note, in this version we are using HSYNC which is the inverse of CSYNC
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.macro WAIT_FOR_CSYNC_0
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WAIT_FOR_HSYNC_1
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.endm
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.macro WAIT_FOR_CSYNC_1
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WAIT_FOR_HSYNC_0
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.endm
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.macro WAIT_FOR_HSYNC_0
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wait\@:
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// Read the GPLEV0
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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bne wait\@
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// Check again in case of noise
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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bne wait\@
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.endm
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.macro WAIT_FOR_HSYNC_1
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wait\@:
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// Read the GPLEV0
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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beq wait\@
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// Check again in case of noise
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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beq wait\@
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.endm
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.macro WAIT_FOR_PSYNC_0
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wait\@:
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// Read the GPLEV0
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ldr r8, [r4]
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tst r8, #PSYNC_MASK
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bne wait\@
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// Check again in case of noise
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ldr r8, [r4]
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tst r8, #PSYNC_MASK
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bne wait\@
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.endm
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.macro WAIT_FOR_PSYNC_1
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wait\@:
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// Read the GPLEV0
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ldr r8, [r4]
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tst r8, #PSYNC_MASK
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beq wait\@
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// Check again in case of noise
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ldr r8, [r4]
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tst r8, #PSYNC_MASK
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beq wait\@
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.endm
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rgb_to_fb:
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push {r4-r12, lr}
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mov r3, r2
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ldr r4, =GPLEV0
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frame:
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// Set framebuffer address
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#ifdef LINE_DOUBLE
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mov r11, r0
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#else
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add r11, r0, r3
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eor r3, r3, r2
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#endif
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// Wait for start of vsync
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wait_for_vsync_a:
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ldr r8, [r4]
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tst r8, #VSYNC_MASK
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beq wait_for_vsync_a
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// Check again in case of noise
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ldr r8, [r4]
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tst r8, #VSYNC_MASK
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beq wait_for_vsync_a
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// Wait for end of vsync
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wait_for_vsync_b:
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ldr r8, [r4]
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tst r8, #VSYNC_MASK
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bne wait_for_vsync_b
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// Check again in case of noise
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ldr r8, [r4]
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tst r8, #VSYNC_MASK
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bne wait_for_vsync_b
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// Working registers in the first half
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//
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// r4 = GPLEV0
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// r5 = time of falling edge
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// r6 = time of rising edge
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// r7 = time of previous rising edge
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// r8 = value read from GPLEV0
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// r9 = state variable (1 = seen a long pulse
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// Enable the cycle counter, and run at the ARM clock rate
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mov r9, #7
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mcr p15, 0, r9, c15, c12, 0
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// Initialize "seen long pulse" to false (0)
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mov r9, #0
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// Wait for csync to be high
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WAIT_FOR_CSYNC_1
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vsync_loop:
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// Wait for the falling edge of csync
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WAIT_FOR_CSYNC_0
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// Record time of the falling edge
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mrc p15, 0, r5, c15, c12, 1
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// Wait for the rising edge of hsync
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WAIT_FOR_CSYNC_1
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// Save time of previous rising edge
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mov r7, r6
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// Record time of the rising edge
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mrc p15, 0, r6, c15, c12, 1
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// Calculate length of low hsync pulse (in ARM cycles = ns)
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sub r5, r6, r5
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// Compare with 6us to descriminate short from long
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// - normal hsync pulses are 4us
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// - during vsync everything is either inverted, or clamped to zero
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// - this results in hsync pulses between 9us and 128us
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cmp r5, #6144
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blt seen_short
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// Set the state variable to indicate we are in the vsync
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mov r9, #1
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// Loop back to wait for the next pulse
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b vsync_loop
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seen_short:
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// Test to see if we've seen any long pulses
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cmp r9, #1
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// No, so look back for the next pulse
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bne vsync_loop
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// Working registers in the second half
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//
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// r4 = GPLEV0
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// r5 = line counter
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// r6 = pixel counter
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// r8 = value read from GPLEV0
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// r9 = extracted pixel
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// r10 = block of 8 pixels, to be written to FB
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// r11 = pointer into frame buffer (start of line)
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// r12 = pointer into frame buffer (moves within line)
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// Set framebuffer address
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mov r11, r0
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// The odd vs even field can be distinguished by the time between
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// the last two rising edges:
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// odd field (first field) should be 23us
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// even field (second field) should be 51us
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sub r6, r6, r7
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cmp r6, #32768
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// For even field, increment the frame buffer pointer by one line
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addge r11, r11, r2
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// Skip inactive lines
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mov r5, #28
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loop0:
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skip_line_loop:
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wait_for_hsync_a:
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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beq wait_for_hsync_a
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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beq wait_for_hsync_a
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wait_for_hsync_b:
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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bne wait_for_hsync_b
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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bne wait_for_hsync_b
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WAIT_FOR_CSYNC_0
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WAIT_FOR_CSYNC_1
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subs r5, r5, #1
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bne loop0
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bne skip_line_loop
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// Process active lines
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mov r5, #256
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loop1:
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process_line_loop:
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// Wait for active high hsync
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wait_for_hsync:
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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beq wait_for_hsync
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ldr r8, [r4]
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tst r8, #HSYNC_MASK
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beq wait_for_hsync
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// Wait for the start of hsync
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WAIT_FOR_CSYNC_0
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// number of 8-bit characters per line
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mov r6, r1
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// pointer into frame buffer
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mov r12, r11
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loop2:
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process_chars_loop:
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// Initialize 8 pixel block
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mov r10, #0
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// Wait for 0-1 edge on PSYNC
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wait_psync_01:
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ldr r8, [r4]
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tst r8, #PSYNC_MASK
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beq wait_psync_01
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ldr r8, [r4]
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tst r8, #PSYNC_MASK
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beq wait_psync_01
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WAIT_FOR_PSYNC_1
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// Pixel 0 in GPIO 4.. 2 -> 7.. 4
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// Pixel 1 in GPIO 7.. 5 -> 3.. 0
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@ -140,13 +215,7 @@ wait_psync_01:
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orr r10, r10, r9, lsr #3
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// Wait for 1-0 edge on PSYNC
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wait_psync_10:
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ldr r8, [r4]
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tst r8, #PSYNC_MASK
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bne wait_psync_10
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ldr r8, [r4]
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tst r8, #PSYNC_MASK
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bne wait_psync_10
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WAIT_FOR_PSYNC_0
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// Pixel 4 in GPIO 4.. 2 -> 23..20
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// Pixel 5 in GPIO 7.. 5 -> 19..16
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@ -165,19 +234,19 @@ wait_psync_10:
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and r9, r8, #(7 << (PIXEL_BASE + 9))
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orr r10, r10, r9, lsl #13
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#ifdef LINE_DOUBLE
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#ifdef LINE_DOUBLE
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str r10, [r12, r2]
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#endif
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#endif
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str r10, [r12], #4
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subs r6, r6, #1
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bne loop2
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bne process_chars_loop
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// Skip a whole line to maintain aspect ratio
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add r11, r11, r2, lsl #1
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subs r5, r5, #1
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bne loop1
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bne process_line_loop
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b frame
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