kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Double buffering now working well in all Modes on Pi Zero
Change-Id: I000aa01c2c7b16926f15016446d39cdef2b8e583issue_1022
David Banks
rodzic
79e23bb3a8
commit
a30c529ac4
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@ -4,7 +4,7 @@
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#define DEFS_H
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// Enable double buffering and vsync based page flipping
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// #define DOUBLE_BUFFER
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#define DOUBLE_BUFFER
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#define VSYNCINT 16
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138
src/rgb_to_fb.S
138
src/rgb_to_fb.S
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@ -1,12 +1,31 @@
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#include "rpi-base.h"
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#include "defs.h"
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// Field State bits (maintained in r3)
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//
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// bit 0 indicates mode 7
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// bit 1 is the buffer being written to
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// bit 2 is the buffer being displayed
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// bit 3 is the field type (0 = odd, 1 = even) of the last field
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#define BIT_MODE7 0x01
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#define BIT_DRAW_BUFFER 0x02
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#define BIT_DISP_BUFFER 0x04
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#define BIT_FIELD_TYPE 0x08
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#define BIT_BOTH_BUFFERS (BIT_DRAW_BUFFER | BIT_DISP_BUFFER)
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#define FIELD_TYPE_THRESHOLD 32768
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.text
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.global rgb_to_fb
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.global measure_vsync
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.macro POLL_VSYNC
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#ifdef DOUBLE_BUFFER
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// Skip the double buffering in mode 7
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tst r3, #BIT_MODE7
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bne novsync\@
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// Poll for the VSYNC interrupt
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ldr r0, =INTPEND2
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ldr r0, [r0]
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@ -17,10 +36,11 @@
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mov r10, #0
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str r10, [r0]
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// Flip the buffers
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// (bit 2 is the draw buffer, bit 3 is the display buffer)
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eor r3, r3, #0x0C
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eor r3, r3, #BIT_BOTH_BUFFERS
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push {r0-r3}
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mov r0, r3, lsr #3
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tst r3, #BIT_DISP_BUFFER
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moveq r0, #0
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movne r0, #1
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bl swapBuffer
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pop {r0-r3}
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novsync\@:
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@ -87,36 +107,38 @@ rgb_to_fb:
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// Save the parameters so the registers can be reused
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str r0, param_framebuffer
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str r3, param_mode7
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#ifdef DOUBLE_BUFFER
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ldr r3, =SCREEN_HEIGHT
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mul r3, r3, r2
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add r0, r3
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ldr r10, =SCREEN_HEIGHT
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mul r10, r10, r2
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add r0, r10
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str r0, param_framebuffer2
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// Default to displaying buffer 0
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push {r0-r3}
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mov r0, #0
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bl swapBuffer
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pop {r0-r3}
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#endif
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bl init_timer_and_io
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bl clear_screen
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// clear all the state bits apart from Mode7
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bic r3, r3, #~BIT_MODE7
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// write to buffer 0, display buffer 1
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mov r3, #8
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orr r3, r3, #BIT_DISP_BUFFER
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frame:
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bl wait_for_vsync
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// Working registers in the second half
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//
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// r0 = unused
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// r0 = scratch register
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// r1 = 8-pixel characters per line (normally 80, but 62.5 (63) in Mode 7
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// r2 = bytes per line
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// r3 = field state:
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// bit 0 is the field type (0 = odd, 1 = even) of the last field
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// bit 1 indicates to line-double this field
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// bit 2 is the buffer being written to
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// bit 3 is the buffer being displayed
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// r3 = field state
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// r4 = GPLEV0
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// r5 = line counter
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// r6 = pixel counter
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@ -128,7 +150,7 @@ frame:
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// Set framebuffer address to the opposite of the buffer being displayed
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#ifdef DOUBLE_BUFFER
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tst r3, #4
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tst r3, #BIT_DRAW_BUFFER
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ldreq r11, param_framebuffer
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ldrne r11, param_framebuffer2
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#else
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@ -141,39 +163,38 @@ frame:
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// even field (second field) should be 53/55us
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sub r6, r6, r7
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// For even field, increment the frame buffer pointer by one line
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cmp r6, #32768
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addge r11, r11, r2
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// Test for non-interlaced by looking for two successive fields of the same type
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// r3 bit 0: 0 (last field odd) or 1 (last field even)
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eorlt r3, r3, #1 // Odd
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tst r3, #1
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// If yes, force line doubling
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biceq r3, r3, #2
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orrne r3, r3, #2
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subne r11, r11, r2
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// Save the current field type
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cmp r6, #32768
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biclt r3, r3, #1 // Odd, clear r3 bit 0
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orrge r3, r3, #1 // Even, set r3 bit 0
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cmp r6, #FIELD_TYPE_THRESHOLD
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biclt r3, r3, #BIT_FIELD_TYPE // Odd, clear bit
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orrge r3, r3, #BIT_FIELD_TYPE // Even, set bit
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// Check for mode change:
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// Odd: Mode 0..6 should be 21us, Mode 7 should be 23us
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// Even: Mode 0..6 should be 53us, Mode 7 should be 55us
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ldrlt r5, =22000 // Use 22us threshold in odd field
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ldrge r5, =54000 // Use 54us threshold in even field
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tst r3, #BIT_FIELD_TYPE
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ldreq r5, =22000 // Use 22us threshold in odd field
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ldrne r5, =54000 // Use 54us threshold in even field
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cmp r6, r5
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movlt r6, #0 // Modes 0-6
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movge r6, #1 // Mode 7
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ldr r5, param_mode7
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cmp r5, r6 // Check if we have changed mode
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movlt r0, #0 // Modes 0-6
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movge r0, #1 // Mode 7
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tst r3, #BIT_MODE7
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moveq r5, #0 // Modes 0-6
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movne r5, #1 // Mode 7
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cmp r5, r0 // Check if we have changed mode
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bne exit // If not, then bail, as clock needs to be changed
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// Skip inactive lines
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mov r5, #NUM_INACTIVE
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// Correct the relative positions of the odd and even frames
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// In Mode 0..6, reduce the number of active lines by one for the even frame
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// In Mode 7, increment the frame buffer pointer by one line for the even field
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tst r3, #BIT_FIELD_TYPE
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beq skip_line_loop
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tst r3, #BIT_MODE7
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subeq r5, r5, #1 // Modes 0-6
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addne r11, r11, r2 // Mode 7
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skip_line_loop:
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POLL_VSYNC
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@ -242,11 +263,11 @@ process_chars_loop:
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and r9, r8, #(7 << (PIXEL_BASE + 9))
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orr r10, r10, r9, lsl #13
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// Line double if non-interlaced and single core Pi
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// Line double always in Modes 0-6 regardless of interlace
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// On the multi core Pi this introduces stalling artefacts
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#ifndef HAS_MULTICORE
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tst r3, #2
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strne r10, [r12, r2]
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#ifndef HAS_MULTICORE
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tst r3, #BIT_MODE7
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streq r10, [r12, r2]
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#endif
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str r10, [r12], #4
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@ -263,7 +284,6 @@ process_chars_loop:
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// Return
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exit:
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mov r0, r6
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pop {r4-r12, lr}
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mov pc, lr
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@ -345,7 +365,7 @@ init_timer_and_io:
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mcr p15, 0, r4, c9, c12, 0
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mov r4, #(1 << 31)
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mcr p15, 0, r4, c9, c12, 1
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#else
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#else
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mov r4, #7
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mcr p15, 0, r4, c15, c12, 0
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#endif
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@ -354,14 +374,14 @@ init_timer_and_io:
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ldr r4, =GPLEV0
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mov pc, lr
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measure_vsync:
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push {r4-r12, lr}
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// Initialize the cycle counter, and set r4=GPLEV0
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bl init_timer_and_io
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// wait for vsync, r6 contains the time of the subsequent hsync rising edge
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bl wait_for_vsync
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mov r0, r6
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@ -371,7 +391,7 @@ measure_vsync:
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// Record field type
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sub r6, r6, r7
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cmp r6, #32768
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cmp r6, #FIELD_TYPE_THRESHOLD
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movlt r3, #0 // Odd
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movge r3, #1 // Even
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@ -383,15 +403,15 @@ measure_vsync:
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// Test for non-interlaced by looking for two successive fields of the same type
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sub r6, r6, r7
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cmp r6, #32768
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cmp r6, #FIELD_TYPE_THRESHOLD
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eorlt r3, r3, #1 // Odd
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tst r3, #1
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// Set bit 31 of result if frame was interlaced
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orreq r0, r0, #INTERLACED_FLAG
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pop {r4-r12, lr}
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mov pc, lr
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clear_screen:
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ldr r11, param_framebuffer
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mov r7, #0
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@ -410,7 +430,7 @@ clear_loop2:
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bne clear_loop1
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mov pc, lr
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param_framebuffer:
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.word 0
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@ -418,7 +438,3 @@ param_framebuffer:
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param_framebuffer2:
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.word 0
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#endif
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param_mode7:
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.word 0
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