13 Commity (5739127412b6756801a38c700d068dd1d937ed41)

Autor	SHA1	Wiadomość	Data
morris	7a71cedf87	interrupt: filter out reserved int number by decoding risc-v JAL instruction	2021-01-05 15:39:46 +08:00
morris	9e7d2c0065	esp32c3: format and clean up interrupt and os port code	2021-01-05 15:39:46 +08:00
Felipe Neves	72e4655d4e	interrupt: removed descriptor table from esp32c3 interrupt hal.	2021-01-05 15:39:46 +08:00
Felipe Neves	544a3f7df5	interrupt-allocator: reject vector allocation if its marked as not-implemented. and search to next available	2021-01-05 15:39:46 +08:00
Felipe Neves	ec5acf91ee	esp_shared_stack: enable shared stack function for riscv and reenable the unit test	2021-01-05 15:39:46 +08:00
Felipe Neves	f4781d3b1d	freertos: riscv port now uses interrupt allocator and crosscore interrupt	2021-01-05 15:39:46 +08:00
Felipe Neves	810be86f21	freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. ... The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.	2021-01-05 15:39:46 +08:00
Omar Chebib	c218f669ba	panic on RISC-V: Take into account Merge Request comments	2020-12-31 15:46:17 +08:00
Omar Chebib	a90dcfba1a	panic: Add support for SoC-level panic ... Activate "invalid access to cache raises panic (PRO CPU)" CI unit test in order to test SoC-level panics.	2020-12-31 15:46:17 +08:00
Omar Chebib	b6a450f824	panic: Add support for SoC-level panic ... SoC level exceptions such as watchdog timer and cache errors are now supported. Such exceptions now triggers a panic, giving more information about how and when it happened.	2020-12-31 15:46:17 +08:00
Angus Gratton	e2d4f0e320	riscv: Place stdatomic file in iram	2020-12-24 14:18:01 +11:00
Renz Bagaporo	4cc6b5571b	esp_system: support riscv panic	2020-11-13 07:49:11 +11:00
Angus Gratton	fccab8f4ef	riscv: Add new arch-level component ... Changes come from internal branch commit a6723fc	2020-11-12 09:33:18 +11:00