kopia lustrzana https://github.com/espressif/esp-idf
interrupt-allocator: reject vector allocation if its marked as not-implemented. and search to next available
rodzic
ec5acf91ee
commit
544a3f7df5
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@ -48,7 +48,7 @@ Define this to debug the choices made when allocating the interrupt. This leads
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output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog
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being triggered, that is why it is separate from the normal LOG* scheme.
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*/
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//define DEBUG_INT_ALLOC_DECISIONS
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//#define DEBUG_INT_ALLOC_DECISIONS
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#ifdef DEBUG_INT_ALLOC_DECISIONS
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# define ALCHLOG(...) ESP_EARLY_LOGD(TAG, __VA_ARGS__)
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#else
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@ -238,13 +238,14 @@ static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force
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return false;
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}
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//Check if the interrupt level is acceptable
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if (!(flags&(1<<interrupt_controller_hal_get_level(x)))) {
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if (!(flags&(1<<interrupt_controller_hal_get_level(x))) &&
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(interrupt_controller_hal_get_type(x)!=INTTP_ANY)) {
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ALCHLOG("....Unusable: incompatible level");
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return false;
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return false;
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}
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//check if edge/level type matches what we want
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if (((flags&ESP_INTR_FLAG_EDGE) && (interrupt_controller_hal_get_type(x)==INTTP_LEVEL)) ||
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(((!(flags&ESP_INTR_FLAG_EDGE)) && (interrupt_controller_hal_get_type(x)==INTTP_EDGE)))) {
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if (((flags&ESP_INTR_FLAG_EDGE) && (interrupt_controller_hal_get_type(x)==INTTP_LEVEL) && (interrupt_controller_hal_get_type(x)!= INTTP_ANY)) ||
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(((!(flags&ESP_INTR_FLAG_EDGE)) && (interrupt_controller_hal_get_type(x)==INTTP_EDGE)&& (interrupt_controller_hal_get_type(x)!= INTTP_ANY)))) {
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ALCHLOG("....Unusable: incompatible trigger type");
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return false;
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}
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@ -582,12 +583,16 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
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esp_intr_disable(ret);
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}
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//Set the level and type at controller level if needed:
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interrupt_controller_hal_set_int_level(intr,
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interrupt_controller_hal_desc_level(intr));
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//Extract the level from the interrupt passed flags
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int level = (__builtin_ffs((flags >> 1) & ESP_INTR_FLAG_LEVELMASK)) + 1;
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interrupt_controller_hal_set_int_type(intr,
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interrupt_controller_hal_desc_type(intr));
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interrupt_controller_hal_set_int_level(intr,level);
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if (flags & ESP_INTR_FLAG_EDGE) {
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interrupt_controller_hal_set_int_type(intr,INTTP_EDGE);
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} else {
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interrupt_controller_hal_set_int_type(intr,INTTP_LEVEL);
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}
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portEXIT_CRITICAL(&spinlock);
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@ -1,2 +0,0 @@
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/* Just a placeholder since this file is exposed in some top-level apps */
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#pragma once
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@ -73,7 +73,7 @@ rtos_int_exit:
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la t2, uxInterruptNesting
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lw t3, 0x0(t2)
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/* Already zero, protect againts underflow */
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/* Already zero, protect against underflow */
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beq t3, zero, isr_skip_decrement
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addi t3,t3, -1
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sw t3, 0x0(t2)
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@ -122,8 +122,7 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
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*/
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static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
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{
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intr_cntrl_ll_disable_interrupts(1 << intr);
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esprv_intc_int_set_priority(intr, 0);
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esprv_intc_set_interrupt_clear(intr);
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}
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/**
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@ -145,9 +144,6 @@ static inline void intr_cntrl_ll_set_int_level(int intr, int level)
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*/
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static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type)
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{
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/* Not needed currently for xtensa platforms since the type is already set
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* in interrupt table
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*/
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esprv_intc_int_set_type(BIT(intr), type);
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}
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@ -18,38 +18,38 @@
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//This is basically a software-readable version of the interrupt usage table in include/soc/soc.h
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const int_desc_t interrupt_descriptor_table[32] = {
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{ 1, INTTP_LEVEL, {INTDESC_RESVD } }, //0
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{ 1, INTTP_LEVEL, {INTDESC_SPECIAL } }, //1
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //2
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //3
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //4
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{ 1, INTTP_LEVEL, {INTDESC_SPECIAL } }, //5
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{ 1, INTTP_NA, {INTDESC_NORMAL } }, //6
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{ 1, INTTP_NA, {INTDESC_NORMAL } }, //7
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{ 1, INTTP_LEVEL, {INTDESC_SPECIAL } }, //8
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{ 1, INTTP_LEVEL, {INTDESC_SPECIAL } }, //9
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{ 1, INTTP_EDGE, {INTDESC_NORMAL } }, //10
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{ 3, INTTP_NA, {INTDESC_NORMAL } }, //11
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{ 1, INTTP_LEVEL, {INTDESC_SPECIAL } }, //12
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //13
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{ 7, INTTP_LEVEL, {INTDESC_NORMAL } }, //14
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{ 3, INTTP_NA, {INTDESC_NORMAL } }, //15
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{ 5, INTTP_NA, {INTDESC_NORMAL } }, //16
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //17
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{ 1, INTTP_LEVEL, {INTDESC_NORMAL } }, //18
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{ 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //19
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{ 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //20
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{ 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //21
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{ 3, INTTP_EDGE, {INTDESC_NORMAL } }, //22
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{ 3, INTTP_LEVEL, {INTDESC_NORMAL } }, //23
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{ 4, INTTP_LEVEL, {INTDESC_RESVD } }, //24
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{ 4, INTTP_LEVEL, {INTDESC_RESVD } }, //25
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{ 5, INTTP_LEVEL, {INTDESC_NORMAL } }, //26
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{ 3, INTTP_LEVEL, {INTDESC_NORMAL } }, //27
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{ 4, INTTP_EDGE, {INTDESC_NORMAL } }, //28
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{ 3, INTTP_NA, {INTDESC_NORMAL } }, //29
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{ 4, INTTP_EDGE, {INTDESC_NORMAL } }, //30
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{ 5, INTTP_LEVEL, {INTDESC_NORMAL } }, //31
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{ 1, INTTP_ANY, {INTDESC_RESVD } }, //0
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{ 1, INTTP_ANY, {INTDESC_SPECIAL } }, //1
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //2
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //3
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //4
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{ 1, INTTP_ANY, {INTDESC_SPECIAL } }, //5
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //6
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //7
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{ 1, INTTP_ANY, {INTDESC_SPECIAL } }, //8
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{ 1, INTTP_ANY, {INTDESC_SPECIAL } }, //9
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //10
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //11
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{ 1, INTTP_ANY, {INTDESC_SPECIAL } }, //12
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //13
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //14
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //15
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //16
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //17
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //18
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //19
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //20
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //21
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //22
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //23
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //24
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //25
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //26
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //27
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //28
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //29
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //30
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{ 1, INTTP_ANY, {INTDESC_NORMAL } }, //31
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};
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const int_desc_t *interrupt_controller_hal_desc_table(void)
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@ -24,13 +24,13 @@ extern "C" {
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typedef enum {
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INTDESC_NORMAL=0,
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INTDESC_RESVD,
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INTDESC_SPECIAL
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INTDESC_SPECIAL,
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} int_desc_flag_t;
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typedef enum {
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INTTP_LEVEL=0,
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INTTP_EDGE,
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INTTP_NA
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INTTP_ANY,
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} int_type_t;
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typedef struct {
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@ -110,6 +110,13 @@ void esprv_intc_set_threshold(int priority_threshold);
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*/
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uint32_t esprv_intc_get_interrupt_unmask(void);
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/**
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* @brief Set a bit in int clear register
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* @param intr bit to set from 0 to 31
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* @return none
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*/
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void esprv_intc_set_interrupt_clear(int intr);
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#ifdef __cplusplus
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}
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#endif
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@ -89,6 +89,12 @@ uint32_t esprv_intc_get_interrupt_unmask(void)
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return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
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}
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void esprv_intc_set_interrupt_clear(int intr)
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{
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REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr);
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}
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/*************************** Exception names. Used in .gdbinit file. ***************************/
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const char *riscv_excp_names[16] __attribute__((used)) = {
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