kopia lustrzana https://github.com/espressif/esp-idf
panic: Add support for SoC-level panic
SoC level exceptions such as watchdog timer and cache errors are now supported. Such exceptions now triggers a panic, giving more information about how and when it happened.pull/6365/head
Omar Chebib
rodzic
e20833124e
commit
b6a450f824
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@ -19,13 +19,81 @@
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data from the bus.
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*/
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "freertos/FreeRTOS.h"
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#include "esp_intr_alloc.h"
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#include "soc/extmem_reg.h"
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#include "soc/periph_defs.h"
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#include "riscv/interrupt.h"
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// TODO ESP32-C3 IDF-2450
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void esp_cache_err_int_init(void)
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{
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const uint32_t core_id = 0;
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/* Disable cache interrupts if enabled. */
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ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
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/**
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* Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with
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* them in handler by different types
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* I) Cache access error
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* 1. dbus trying to write to icache
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* 2. dbus authentication fail
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* 3. cpu access icache while dbus is disabled [1]
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* 4. ibus authentication fail
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* 5. ibus trying to write icache
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* 6. cpu access icache while ibus is disabled
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* II) Cache illegal error
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* 1. dbus counter overflow
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* 2. ibus counter overflow
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* 3. mmu entry fault
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* 4. icache preload configurations fault
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* 5. icache sync configuration fault
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*
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* [1]: On ESP32C3 boards, the caches are shared but buses are still
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* distinct. So, we have an ibus and a dbus sharing the same cache.
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* This error can occur if the dbus performs a request but the icache
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* (or simply cache) is disabled.
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*/
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intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
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intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
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/* Set the type and priority to cache error interrupts. */
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esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL);
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esprv_intc_int_set_priority(ETS_CACHEERR_INUM, 4);
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/* On the hardware side, stat by clearing all the bits reponsible for
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* enabling cache access error interrupts. */
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SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG,
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EXTMEM_CORE0_DBUS_WR_IC_INT_CLR |
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EXTMEM_CORE0_DBUS_REJECT_INT_CLR |
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EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR |
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EXTMEM_CORE0_IBUS_REJECT_INT_CLR |
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EXTMEM_CORE0_IBUS_WR_IC_INT_CLR |
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EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR);
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/* Enable these interrupts. */
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SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG,
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EXTMEM_CORE0_DBUS_WR_IC_INT_ENA |
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EXTMEM_CORE0_DBUS_REJECT_INT_ENA |
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EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA |
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EXTMEM_CORE0_IBUS_REJECT_INT_ENA |
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EXTMEM_CORE0_IBUS_WR_IC_INT_ENA |
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EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA);
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/* Same goes for cache illegal error: start by clearing the bits and then
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* set them back. */
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SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG,
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EXTMEM_MMU_ENTRY_FAULT_INT_CLR |
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EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR |
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EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR);
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SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG,
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EXTMEM_MMU_ENTRY_FAULT_INT_ENA |
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EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA |
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EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA);
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/* Enable the interrupts for cache error. */
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ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
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}
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int IRAM_ATTR esp_cache_err_get_cpuid(void)
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@ -31,6 +31,7 @@
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#include "esp_private/system_internal.h"
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#include "hal/timer_types.h"
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#include "hal/wdt_hal.h"
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#include "hal/interrupt_controller_hal.h"
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#if CONFIG_ESP_INT_WDT
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@ -106,6 +107,7 @@ void esp_int_wdt_init(void) {
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wdt_hal_write_protect_disable(&iwdt_context);
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//The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
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//it to their actual value.
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//1st stage timeout: interrupt
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);
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//2nd stage timeout: reset system
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@ -121,6 +123,16 @@ void esp_int_wdt_cpu_init(void)
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esp_register_freertos_tick_hook_for_cpu(tick_hook, xPortGetCoreID());
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ESP_INTR_DISABLE(WDT_INT_NUM);
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intr_matrix_set(xPortGetCoreID(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
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/* Set the type and priority to cache error interrupts, if supported. */
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#if SOC_INTERRUPT_TYPE_CAN_SET
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interrupt_controller_hal_set_type(BIT(WDT_INT_NUM), INTR_TYPE_LEVEL);
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#endif
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#if SOC_INTERRUPT_LEVEL_CAN_SET
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interrupt_controller_hal_set_level(WDT_INT_NUM, 4);
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#endif
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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/*
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* This is a workaround for issue 3.15 in "ESP32 ECO and workarounds for
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@ -133,6 +145,7 @@ void esp_int_wdt_cpu_init(void)
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_l4_intr_livelock_max = CONFIG_ESP_INT_WDT_TIMEOUT_MS/IWDT_LIVELOCK_TIMEOUT_MS - 1;
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}
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#endif
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//We do not register a handler for the interrupt because it is interrupt level 4 which
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//is not servicable from C. Instead, xtensa_vectors.S has a call to the panic handler for
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//this interrupt.
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@ -14,10 +14,136 @@
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// limitations under the License.
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#include <stdio.h>
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#include "soc/extmem_reg.h"
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#include "esp_private/panic_internal.h"
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#include "esp_private/panic_reason.h"
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#include "riscv/rvruntime-frames.h"
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extern void esp_panic_handler(panic_info_t *);
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#if CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/cache_err_int.h"
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#endif
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#define DIM(array) (sizeof(array)/sizeof(*array))
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/**
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* Structure used to define a flag/bit to test in case of cache error.
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* The message describes the cause of the error when the bit is set in
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* a given status register.
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*/
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typedef struct {
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const uint32_t bit;
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const char* msg;
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} register_bit_t;
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/**
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* Function to check each bits defined in the array reg_bits in the given
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* status register. The first bit from the array to be set in the status
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* register will have its associated message printed. This function returns
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* true. If not bit was set in the register, it returns false.
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* The order of the bits in the array is important as only the first bit to
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* be set in the register will have its associated message printed.
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*/
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static inline bool test_and_print_register_bits(const uint32_t status,
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const register_bit_t* reg_bits,
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const uint32_t size)
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{
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/* Browse the flag/bit array and test each one with the given status
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* register. */
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for (int i = 0; i < size; i++) {
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const uint32_t bit = reg_bits[i].bit;
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if ((status & bit) == bit) {
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/* Reason of the panic found, print the reason. */
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panic_print_str(reg_bits[i].msg);
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panic_print_str("\r\n");
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return true;
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}
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}
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/* Panic cause not found, no message was printed. */
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return false;
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}
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/**
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* Function called when a cache error occurs. It prints details such as the
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* explanation of why the panic occured.
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*/
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static inline void print_cache_err_details(const void* frame)
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{
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/* Define the array that contains the status (bits) to test on the register
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* EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. each bit is accompanied by a small
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* message.
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* The messages have been pulled from the header file where the status bit
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* are defined. */
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const register_bit_t core0_acs_bits[] = {
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{
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.bit = EXTMEM_CORE0_DBUS_WR_ICACHE_ST,
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.msg = "dbus tried to write cache"
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},
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{
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.bit = EXTMEM_CORE0_DBUS_REJECT_ST,
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.msg = "dbus authentication failed"
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},
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{
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.bit = EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST,
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.msg = "access to cache while dbus or cache is disabled"
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},
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{
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.bit = EXTMEM_CORE0_IBUS_REJECT_ST,
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.msg = "ibus authentication failed"
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},
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{
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.bit = EXTMEM_CORE0_IBUS_WR_ICACHE_ST,
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.msg = "ibus tried to write cache"
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},
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{
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.bit = EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST,
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.msg = "access to cache while ibus or cache is disabled"
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},
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};
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/* Same goes for the register EXTMEM_CACHE_ILG_INT_ST_REG and its bits. */
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const register_bit_t cache_ilg_bits[] = {
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{
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.bit = EXTMEM_MMU_ENTRY_FAULT_ST,
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.msg = "MMU entry fault"
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},
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{
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.bit = EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST,
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.msg = "preload configurations fault"
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},
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{
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.bit = EXTMEM_ICACHE_SYNC_OP_FAULT_ST,
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.msg = "sync configurations fault"
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},
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};
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/* Read the status register EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. This status
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* register is not equal to 0 when a cache access error occured. */
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const uint32_t core0_status = REG_READ(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG);
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/* If the panic is due to a cache access error, one of the bit of the
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* register is set. Thus, this function will return true. */
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bool handled = test_and_print_register_bits(core0_status, core0_acs_bits, DIM(core0_acs_bits));
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/* If the panic was due to a cache illegal error, the previous call returned false and this
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* EXTMEM_CACHE_ILG_INT_ST_REG register should not me equal to 0.
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* Check each bit of it and print the message associated if found. */
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if (!handled) {
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const uint32_t cache_ilg_status = REG_READ(EXTMEM_CACHE_ILG_INT_ST_REG);
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handled = test_and_print_register_bits(cache_ilg_status, cache_ilg_bits, DIM(cache_ilg_bits));
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/* If the error was not found, print the both registers value */
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if (!handled) {
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panic_print_str("EXTMEM_CORE0_ACS_CACHE_INT_ST_REG = 0x");
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panic_print_hex(core0_status);
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panic_print_str("\r\nEXTMEM_CACHE_ILG_INT_ST_REG = 0x");
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panic_print_hex(cache_ilg_status);
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panic_print_str("\r\n");
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}
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}
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}
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void panic_print_registers(const void *f, int core)
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{
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@ -49,10 +175,48 @@ void panic_print_registers(const void *f, int core)
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}
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}
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/**
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* This function will be called when a SoC-level panic occurs.
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* SoC-level panics include cache errors and watchdog interrupts.
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*/
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void panic_soc_fill_info(void *f, panic_info_t *info)
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{
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// TODO ESP32-C3 IDF-2386 / support soc panic
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return;
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RvExcFrame *frame = (RvExcFrame *) f;
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/* Please keep in sync with PANIC_RSN_* defines */
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static const char *pseudo_reason[PANIC_RSN_MAX + 1] = {
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"Unknown reason",
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"Interrupt wdt timeout on CPU0",
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"Interrupt wdt timeout on CPU1",
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"Cache exception",
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};
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info->reason = pseudo_reason[0];
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info->addr = (void *) frame->mepc;
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/* The mcause has been set by the CPU when the panic occured.
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* All SoC-level panic will call this function, thus, this register
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* lets us know which error was triggered. */
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if (frame->mcause == ETS_CACHEERR_INUM) {
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/* Panic due to a cache error, multiple cache error are possible,
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* assign function print_cache_err_details to our structure's
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* details field. As its name states, it will give more details
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* about why the error happened. */
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info->core = esp_cache_err_get_cpuid();
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info->reason = pseudo_reason[PANIC_RSN_CACHEERR];
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info->details = print_cache_err_details;
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} else if (frame->mcause == ETS_T1_WDT_INUM) {
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/* Watchdog interrupt occured, get the core on which it happened
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* and update the reason/message accordingly. */
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const int core = esp_cache_err_get_cpuid();
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info->core = core;
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info->exception = PANIC_EXCEPTION_TWDT;
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_Static_assert(PANIC_RSN_INTWDT_CPU0 + 1 == PANIC_RSN_INTWDT_CPU1,
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"PANIC_RSN_INTWDT_CPU1 must be equal to PANIC_RSN_INTWDT_CPU0 + 1");
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info->reason = pseudo_reason[PANIC_RSN_INTWDT_CPU0 + core];
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}
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}
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void panic_arch_fill_info(void *frame, panic_info_t *info)
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@ -115,6 +115,8 @@ static void frame_to_panic_info(void *frame, panic_info_t *info, bool pseudo_exc
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static void panic_handler(void *frame, bool pseudo_excause)
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{
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panic_info_t info = { 0 };
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/*
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* Setup environment and perform necessary architecture/chip specific
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* steps here prior to the system panic handler.
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@ -178,7 +180,6 @@ static void panic_handler(void *frame, bool pseudo_excause)
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}
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// Convert architecture exception frame into abstracted panic info
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panic_info_t info;
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frame_to_panic_info(frame, &info, pseudo_excause);
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// Call the system panic handler
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@ -115,6 +115,29 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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}
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/**
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* @brief Set the interrupt type given an interrupt number.
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*
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* @param interrupt_number number of the interrupt
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* @param type new type for this interrupt
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*/
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static inline void intr_cntrl_ll_set_type(int interrupt_number, int_type_t type)
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{
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esprv_intc_int_set_type(BIT(interrupt_number), type);
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}
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/**
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* @brief Set the interrupt level (priority) given an interrupt number.
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*
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* @param interrupt_number number of the interrupt
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* @param level new level for this interrupt
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*/
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static inline void intr_cntrl_ll_set_level(int interrupt_number, int level)
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{
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esprv_intc_int_set_priority(interrupt_number, level);
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}
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#ifdef __cplusplus
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}
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#endif
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@ -45,8 +45,8 @@ const int_desc_t interrupt_descriptor_table[32] = {
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{ 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //21
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{ 3, INTTP_EDGE, {INTDESC_NORMAL } }, //22
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{ 3, INTTP_LEVEL, {INTDESC_NORMAL } }, //23
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{ 4, INTTP_LEVEL, {INTDESC_NORMAL } }, //24
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{ 4, INTTP_LEVEL, {INTDESC_NORMAL } }, //25
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{ 4, INTTP_LEVEL, {INTDESC_RESVD } }, //24
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{ 4, INTTP_LEVEL, {INTDESC_RESVD } }, //25
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{ 5, INTTP_LEVEL, {INTDESC_NORMAL } }, //26
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{ 3, INTTP_LEVEL, {INTDESC_NORMAL } }, //27
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{ 4, INTTP_EDGE, {INTDESC_NORMAL } }, //28
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@ -17,6 +17,7 @@
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#include <stdbool.h>
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#include "hal/interrupt_controller_types.h"
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#include "hal/interrupt_controller_ll.h"
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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@ -54,6 +55,24 @@ __attribute__((pure)) int interrupt_controller_hal_desc_level(int interrupt_num
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*/
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__attribute__((pure)) int_desc_flag_t interrupt_controller_hal_desc_flags(int interrupt_number, int cpu_number);
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#if CONFIG_IDF_TARGET_ARCH_RISCV
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/**
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* @brief Set the interrupt level given an interrupt number.
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*
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* @param interrupt_number number of the interrupt
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* @param level new level for this interrupt
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*/
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void interrupt_controller_hal_set_level(int interrupt_number, int level);
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/**
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* @brief Set the interrupt type given an interrupt number.
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*
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* @param interrupt_number number of the interrupt
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* @param type new type for this interrupt
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*/
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void interrupt_controller_hal_set_type(int interrupt_number, int_type_t type);
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#endif
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/**
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* @brief Gets the interrupt type given an interrupt number.
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*
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@ -31,3 +31,19 @@ int_desc_flag_t interrupt_controller_hal_desc_flags(int interrupt_number, int cp
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const int_desc_t *int_desc = interrupt_controller_hal_desc_table();
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return(int_desc[interrupt_number].cpuflags[cpu_number]);
|
||||
}
|
||||
|
||||
#if SOC_INTERRUPT_LEVEL_CAN_SET
|
||||
|
||||
void interrupt_controller_hal_set_level(int interrupt_number, int level) {
|
||||
intr_cntrl_ll_set_level(interrupt_number, level);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if SOC_INTERRUPT_TYPE_CAN_SET
|
||||
|
||||
void interrupt_controller_hal_set_type(int interrupt_number, int_type_t type) {
|
||||
intr_cntrl_ll_set_type(interrupt_number, type);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
|
||||
.equ SAVE_REGS, 32
|
||||
.equ CONTEXT_SIZE, (SAVE_REGS * 4)
|
||||
.equ exception_from_panic, xt_unhandled_exception
|
||||
.equ exception_from_isr, panicHandler
|
||||
|
||||
.macro save_regs
|
||||
addi sp, sp, -CONTEXT_SIZE
|
||||
|
|
@ -119,15 +121,20 @@
|
|||
_vector_table:
|
||||
.option push
|
||||
.option norvc
|
||||
j _panic_handler /* exception handler, entry 0 */
|
||||
.rept 31
|
||||
j _interrupt_handler /* 31 identical entries, all pointing to the interrupt handler */
|
||||
j _panic_handler /* exception handler, entry 0 */
|
||||
.rept 23
|
||||
j _interrupt_handler /* 24 identical entries, all pointing to the interrupt handler */
|
||||
.endr
|
||||
j _panic_handler /* Call panic handler for ETS_T1_WDT_INUM interrupt (soc-level panic)*/
|
||||
j _panic_handler /* Call panic handler for ETS_CACHEERR_INUM interrupt (soc-level panic)*/
|
||||
.rept 6
|
||||
j _interrupt_handler /* 6 identical entries, all pointing to the interrupt handler */
|
||||
.endr
|
||||
|
||||
.option pop
|
||||
.size _vector_table, .-_vector_table
|
||||
|
||||
/* Exception handler.*/
|
||||
.global xt_unhandled_exception
|
||||
.type _panic_handler, @function
|
||||
_panic_handler:
|
||||
addi sp, sp, -RV_STK_FRMSZ /* allocate space on stack to store necessary registers */
|
||||
|
|
@ -170,19 +177,34 @@ _panic_handler:
|
|||
sw t0, RV_STK_MSTATUS(sp)
|
||||
csrr t0, mtvec
|
||||
sw t0, RV_STK_MTVEC(sp)
|
||||
csrr t0, mcause
|
||||
sw t0, RV_STK_MCAUSE(sp)
|
||||
csrr t0, mtval
|
||||
sw t0, RV_STK_MTVAL(sp)
|
||||
csrr t0, mhartid
|
||||
sw t0, RV_STK_MHARTID(sp)
|
||||
|
||||
/* call xt_unhandled_exception(sp,cause) */
|
||||
/* Call exception_from_panic(sp) or exception_from_isr(sp)
|
||||
* depending on whether we have a pseudo excause or not.
|
||||
* If mcause's highest bit is 1, then an interrupt called this routine,
|
||||
* so we have a pseudo excause. Else, it is due to a panic, we don't have
|
||||
* an excause */
|
||||
mv a0, sp
|
||||
csrr a1, mcause
|
||||
jal zero, xt_unhandled_exception
|
||||
/* panicHandler never returns */
|
||||
.size _panic_handler, .-_panic_handler
|
||||
/* Branches instructions don't accept immediates values, so use t1 to store
|
||||
* our comparator */
|
||||
li t0, 0x80000000
|
||||
bgeu a1, t0, _call_panic_handler
|
||||
sw a1, RV_STK_MCAUSE(sp)
|
||||
/* exception_from_panic never returns */
|
||||
j exception_from_panic
|
||||
_call_panic_handler:
|
||||
/* Remove highest bit from mcause (a1) register and save it in the
|
||||
* structure */
|
||||
not t0, t0
|
||||
and a1, a1, t0
|
||||
sw a1, RV_STK_MCAUSE(sp)
|
||||
/* exception_from_isr never returns */
|
||||
j exception_from_isr
|
||||
.size exception_from_isr, .-exception_from_isr
|
||||
|
||||
/* This is the interrupt handler.
|
||||
* It saves the registers on the stack,
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue