kopia lustrzana https://github.com/espressif/esp-idf
panic on RISC-V: Take into account Merge Request comments
rodzic
5962b1dc56
commit
c218f669ba
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@ -18,8 +18,8 @@
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to panic the CPU, which from a debugging perspective is better than grabbing bad
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data from the bus.
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*/
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#include "freertos/FreeRTOS.h"
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#include "esp32c3/rom/ets_sys.h"
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#include "esp_attr.h"
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#include "esp_intr_alloc.h"
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#include "soc/extmem_reg.h"
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#include "soc/periph_defs.h"
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@ -184,11 +184,13 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
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RvExcFrame *frame = (RvExcFrame *) f;
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/* Please keep in sync with PANIC_RSN_* defines */
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static const char *pseudo_reason[PANIC_RSN_MAX + 1] = {
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static const char *pseudo_reason[PANIC_RSN_COUNT] = {
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"Unknown reason",
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"Interrupt wdt timeout on CPU0",
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#if SOC_CPU_NUM > 1
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"Interrupt wdt timeout on CPU1",
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"Cache exception",
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#endif
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"Cache error"
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};
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info->reason = pseudo_reason[0];
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@ -213,8 +215,10 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
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info->core = core;
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info->exception = PANIC_EXCEPTION_TWDT;
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#if SOC_CPU_NUM > 1
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_Static_assert(PANIC_RSN_INTWDT_CPU0 + 1 == PANIC_RSN_INTWDT_CPU1,
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"PANIC_RSN_INTWDT_CPU1 must be equal to PANIC_RSN_INTWDT_CPU0 + 1");
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#endif
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info->reason = pseudo_reason[PANIC_RSN_INTWDT_CPU0 + core];
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}
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}
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@ -411,7 +411,7 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
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#if CONFIG_IDF_TARGET_ESP32
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"Cache disabled but cached memory region accessed",
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#elif CONFIG_IDF_TARGET_ESP32S2
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"Cache exception",
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"Cache error",
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#endif
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};
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@ -179,8 +179,12 @@ static void panic_handler(void *frame, bool pseudo_excause)
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panic_set_address(frame, (uint32_t)&_invalid_pc_placeholder);
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}
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#endif
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if (panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU0 ||
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panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU1) {
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if (panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU0
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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|| panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU1
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#endif
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)
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{
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wdt_hal_write_protect_disable(&wdt0_context);
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wdt_hal_handle_intr(&wdt0_context);
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wdt_hal_write_protect_enable(&wdt0_context);
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@ -55,7 +55,7 @@ __attribute__((pure)) int interrupt_controller_hal_desc_level(int interrupt_num
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*/
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__attribute__((pure)) int_desc_flag_t interrupt_controller_hal_desc_flags(int interrupt_number, int cpu_number);
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#if CONFIG_IDF_TARGET_ARCH_RISCV
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#if SOC_INTERRUPT_LEVEL_CAN_SET
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/**
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* @brief Set the interrupt level given an interrupt number.
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*
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@ -13,8 +13,12 @@
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// limitations under the License.
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#pragma once
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#define PANIC_RSN_NONE 0
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#define PANIC_RSN_INTWDT_CPU0 1
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#define PANIC_RSN_INTWDT_CPU1 2
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#define PANIC_RSN_CACHEERR 3
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#define PANIC_RSN_MAX 3
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enum _panic_reasons {
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PANIC_RSN_NONE = 0,
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PANIC_RSN_INTWDT_CPU0,
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#if SOC_CPU_NUM > 1
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PANIC_RSN_INTWDT_CPU1,
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#endif
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PANIC_RSN_CACHEERR,
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PANIC_RSN_COUNT
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} panic_reasons;
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@ -18,8 +18,8 @@
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.equ SAVE_REGS, 32
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.equ CONTEXT_SIZE, (SAVE_REGS * 4)
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.equ exception_from_panic, xt_unhandled_exception
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.equ exception_from_isr, panicHandler
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.equ panic_from_exception, xt_unhandled_exception
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.equ panic_from_isr, panicHandler
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.macro save_regs
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addi sp, sp, -CONTEXT_SIZE
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@ -182,20 +182,20 @@ _panic_handler:
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csrr t0, mhartid
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sw t0, RV_STK_MHARTID(sp)
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/* Call exception_from_panic(sp) or exception_from_isr(sp)
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/* Call panic_from_exception(sp) or panic_from_isr(sp)
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* depending on whether we have a pseudo excause or not.
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* If mcause's highest bit is 1, then an interrupt called this routine,
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* so we have a pseudo excause. Else, it is due to a panic, we don't have
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* an excause */
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* so we have a pseudo excause. Else, it is due to a exception, we don't
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* have an pseudo excause */
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mv a0, sp
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csrr a1, mcause
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/* Branches instructions don't accept immediates values, so use t1 to store
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* our comparator */
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/* Branches instructions don't accept immediates values, so use t1 to
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* store our comparator */
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li t0, 0x80000000
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bgeu a1, t0, _call_panic_handler
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sw a1, RV_STK_MCAUSE(sp)
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/* exception_from_panic never returns */
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j exception_from_panic
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j panic_from_exception
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_call_panic_handler:
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/* Remove highest bit from mcause (a1) register and save it in the
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* structure */
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@ -203,8 +203,8 @@ _call_panic_handler:
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and a1, a1, t0
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sw a1, RV_STK_MCAUSE(sp)
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/* exception_from_isr never returns */
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j exception_from_isr
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.size exception_from_isr, .-exception_from_isr
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j panic_from_isr
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.size panic_from_isr, .-panic_from_isr
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/* This is the interrupt handler.
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* It saves the registers on the stack,
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@ -51,19 +51,10 @@ TEST_CASE("spi_flash_cache_enabled() works on both CPUs", "[spi_flash][esp_flash
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vQueueDelete(result_queue);
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}
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/**
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* On ESP32-C3 boards, constant data with a size less or equal to 8 bytes
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* (64 bits) are placed in the DRAM.
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* Let's add a third unused element to this array to force it to the DROM.
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*/
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static const uint32_t s_in_rodata[] = { 0x12345678, 0xfedcba98, 0x42 };
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static const uint32_t s_in_rodata[] = { 0x12345678, 0xfedcba98 };
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static void IRAM_ATTR cache_access_test_func(void* arg)
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{
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/* Assert that the array s_in_rodata is in DROM. If not, this test is
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* invalid as disabling the cache wouldn't have any effect. */
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TEST_ASSERT(esp_ptr_in_drom(s_in_rodata));
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spi_flash_disable_interrupts_caches_and_other_cpu();
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volatile uint32_t* src = (volatile uint32_t*) s_in_rodata;
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uint32_t v1 = src[0];
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@ -74,15 +65,9 @@ static void IRAM_ATTR cache_access_test_func(void* arg)
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vTaskDelete(NULL);
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}
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#ifdef CONFIG_IDF_TARGET_ESP32C3
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#define CACHE_ERROR_REASON "Cache exception,RTC_SW_CPU_RST"
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#else
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#define CACHE_ERROR_REASON "Cache disabled,SW_RESET"
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#endif
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// These tests works properly if they resets the chip with the
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// "Cache disabled but cached memory region accessed" reason and the correct CPU is logged.
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TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][reset="CACHE_ERROR_REASON"]")
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TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][ignore]")
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{
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xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0);
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vTaskDelay(1000/portTICK_PERIOD_MS);
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@ -90,7 +75,7 @@ TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][reset="
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#ifndef CONFIG_FREERTOS_UNICORE
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TEST_CASE("invalid access to cache raises panic (APP CPU)", "[spi_flash][reset=TG1WDT_SYS_RESET]")
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TEST_CASE("invalid access to cache raises panic (APP CPU)", "[spi_flash][ignore]")
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{
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xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 1);
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vTaskDelay(1000/portTICK_PERIOD_MS);
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