6b96534c68
bugfix: esprv_intc_int_set_type() should not use bitmap parameter
2022-10-14 11:31:22 +08:00
4dddb6d8e8
fix system not stable bug when dbias storing in efuse is bigger than 27
2022-09-30 19:24:51 +08:00
23e37393a7
esp32c6: add esp_hw_support
2022-09-26 20:32:13 +08:00
05a2fbe810
esp_hw_support/clk_cali: fix xtal32k error detect
2022-09-21 03:03:25 +00:00
e7dbfd65cb
Merge branch 'feature/support_7.2.8_soc/pvt-dig' into 'master'
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rtc: auto adjust LDO voltage based on pvt-dig saved in efuse
Closes IDF-4873
See merge request espressif/esp-idf!16365
2022-08-22 11:43:07 +08:00
304a8f142d
esp32c6: introduce the target
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Add esp32c6 target to tools and Kconfig
Create directories and files that are essential for `idf.py --preview set-target esp32c6`
2022-08-19 11:13:02 +08:00
80c821a9aa
1.add ldo parameters in efuse table; 2.set ldo based on pvt-efuse; 3.ldo voltage is changed based on cpu freq
2022-08-15 18:03:55 +08:00
c70094f64a
esp32c2/clk_cali: fix rtc slow clk cali logic
2022-08-15 16:31:54 +08:00
c25c254666
Merge branch 'feature/further_support_esp32c2_sleep' into 'master'
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esp32c2/sleep: further support sleep for esp32c2 with 26MHz XTAL
Closes IDF-5544
See merge request espressif/esp-idf!19017
2022-08-08 13:26:15 +08:00
ee3423834e
kconfig: refactor xtal freq kconfig to common configuration item
2022-08-05 19:12:29 +08:00
7d8f10423e
1.add ldo parameters in efuse table; 2.set ldo dbias based on pvt-efuse; 3.add pll cali stop function; 4. add efuse_ocode
2022-08-05 14:24:51 +08:00
842efaf753
Merge branch 'bugfix/rtc_fastmem_lpu_c3_h2' into 'master'
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sleep: fix wrong register access to set/clear rtc fast mem low power mode on c3 and h2
Closes IDF-5746
See merge request espressif/esp-idf!19361
2022-08-03 19:52:24 +08:00
307d26659e
Merge branch 'bugfix/rmt_hw_issue' into 'master'
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rmt: only use register to control the IDLE state (hardware issue workaround)
See merge request espressif/esp-idf!19344
2022-08-03 17:01:44 +08:00
e8915e14e7
esp_hw_support: fix wrong register access to set/clear rtc fast mem low power mode on c3 and h2
2022-08-03 14:33:13 +08:00
45524408df
coverity: fix uninit variable issue in driver
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Related CID:
389832, 389838, 389880, 286743, 286752, 395156, 291011, 396001, 396002
2022-08-03 10:46:50 +08:00
031adc01c4
gpio: add test with -O0
2022-08-02 23:07:06 +08:00
5e6a16380a
esp_adc: move adc common hw related code into esp_hw_support
2022-07-28 03:49:48 +00:00
5e50ec1d66
systimer: add helper functions to convert between tick and us
2022-07-25 16:08:52 +08:00
0bac33ed41
esp_system: Remove deprecate section from esp_cpu.h
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- Remove esp_cpu_in_ocd_mode() from esp_cpu.h. Users should call esp_cpu_dbgr_is_attached() instead.
- Remove esp_cpu_get_ccount() from esp_cpu.h. Users should call esp_cpu_get_cycle_count() instead.
- Remove esp_cpu_set_ccount() from esp_cpu.h. Users should call esp_cpu_set_cycle_count() instead.
- Other IDF components updated to call esp_cpu_dbgr_is_attached(), esp_cpu_get_cycle_count() and esp_cpu_set_cycle_count() as well.
2022-07-22 00:06:06 +08:00
6005cc9163
hal: Deprecate interrupt_controller_hal.h, cpu_hal.h and cpu_ll.h interfaces
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This commit marks all functions in interrupt_controller_hal.h, cpu_ll.h and cpu_hal.h as deprecated.
Users should use functions from esp_cpu.h instead.
2022-07-22 00:06:06 +08:00
20e21fb29d
Merge branch 'refactor/remove_rom_deps' into 'master'
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RFC: remove dependency to target-specific ROM headers
Closes IDF-1968
See merge request espressif/esp-idf!18206
2022-07-13 16:44:44 +08:00
b610b47a83
Merge branch 'feature/esp32s3_memprot_additional_improvements' into 'master'
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[System/Security] Memprot after-merge improvements (v5.0)
Closes IDF-5263 and IDF-5208
See merge request espressif/esp-idf!18893
2022-07-13 15:48:20 +08:00
33a3616635
refactor (bootloader_support, efuse)!: remove target-specific rom includes
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The following two functions in bootloader_support are private now:
* esp_secure_boot_verify_sbv2_signature_block()
* esp_secure_boot_verify_rsa_signature_block()
They have been moved into private header files
inside bootloader_private/
* Removed bootloader_reset_reason.h and
bootloader_common_get_reset_reason() completely.
Alternative in ROM component is available.
* made esp_efuse.h independent of target-specific rom header
2022-07-13 10:29:02 +08:00
ef813b23fa
rtc: esp32c2 support 26MHz xtal in startup code and rtc_clk.c
2022-07-11 12:24:58 +08:00
0c87ae2a91
System/Security: Memprot API unified (ESP32S3)
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Added missing features and improvements
2022-07-09 22:57:51 +02:00
672e70a023
esp_hw_support: add 26 MHz XTAL option for esp32c2
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Some esp32c2 boards will be produced with a 26 MHz XTAL. This commit
adds the basic Kconfig option for this type of hardware.
Support for CONFIG_ESP32C2_XTAL_FREQ_26 in other areas of IDF will be
implemented in subsequent commits.
2022-07-08 15:04:17 +08:00
a58362a429
Merge branch 'feature/efuse_rev_major_minor' into 'master'
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efuse: Adds major and minor versions
See merge request espressif/esp-idf!18255
2022-07-07 11:48:54 +08:00
b662f4b74f
Merge branch 'feature/support_26M_32M_xtal_bbpll_c2' into 'master'
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support c2 26M/32M xtal for bbpll
Closes IDF-5485
See merge request espressif/esp-idf!18769
2022-07-06 21:17:52 +08:00
e16165f263
support c2 26M/32M xtal for bbpll
2022-07-05 17:45:03 +08:00
0f8ff5aa15
efuse: Adds major and minor versions and others
2022-07-05 14:38:27 +08:00
29c0703d7e
Merge branch 'bugfix/esp32s3_memprot_wrong_check_unicore' into 'master'
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System/Security: fix missing checks for CPU-count sensitive Memprot APIs (ESP32S3)
Closes IDF-5401
See merge request espressif/esp-idf!18834
2022-07-04 16:41:45 +08:00
7e42038c86
Merge branch 'refactor/move_regi2c_headers' into 'master'
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Refactor: move regi2c_*.h header files from esp_hw_support to soc component
See merge request espressif/esp-idf!18676
2022-07-04 11:32:30 +08:00
ee9aa9a302
System/Security: fix missing checks for CPU-count sensitive Memprot APIs (ESP32S3)
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Some of the Memory Protection (internal) API functions dealing with per-CPU operations were missing appropriate handling of the CPU count actually configured by CONFIG_FREERTOS_UNICORE. The flaw was fixed across all the places found in the code as the issue was of general type
2022-07-02 20:12:56 +00:00
a690a87829
spi_flash: Remove legacy spi_flash drivers
2022-07-01 11:01:34 +08:00
cd48baf979
Refactor: move regi2c_*.h header files from esp_hw_support to soc component
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When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.
2022-06-30 09:40:44 +00:00
7fd9a91034
dma: move from driver to hw_support
2022-06-28 14:17:12 +08:00
8fae0f0753
G0: Support Xtensa targets for G0-only compilation
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G0-only example now supports Xtensa targets. This means that G0 layer
does not depend on G1+ layers anymore
2022-06-20 11:34:20 +00:00
339fcbf14d
System/Security: Memprot API unified (ESP32S3)
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Unified Memory protection API for all PMS-aware chips - ESP32S3 port
2022-06-20 02:36:44 +00:00
752026a174
Merge branch 'refactor/remove_g0_dep_on_g1_riscv' into 'master'
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G0: RISC-V targets have now an independent G0 layer
See merge request espressif/esp-idf!17926
2022-06-16 11:53:39 +08:00
0b80546f8e
Merge branch 'feature/new_esp_psram_component' into 'master'
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esp_psram: new esp psram component
Closes IDF-4318, IDF-4382, IDF-4841, and IDFGH-7192
See merge request espressif/esp-idf!18050
2022-06-15 19:16:56 +08:00
e213e66ba3
Merge branch 'refactor/esp_hw_support_cpu' into 'master'
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esp_hw_support: Add new esp_cpu.h abstraction
Closes IDF-4769
See merge request espressif/esp-idf!17091
2022-06-14 21:11:30 +08:00
cdad8a02fe
esp_psram: remove g_spiram_ok
2022-06-14 15:44:27 +08:00
38e5043ae8
esp_psram: new psram component
2022-06-14 15:44:27 +08:00
2fd784c97a
G0 RISC-V: Remove "private_include/regi2c_brownout.h" header as it has been moved and simplify "regi2c_ctrl.h"
2022-06-14 15:00:53 +08:00
5bcd9b2db8
G0: RISC-V targets have now an independent G0 layer
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G0 doesn't depend on any G1+ layer for RISC-V based targets
2022-06-14 15:00:53 +08:00
61eb7baa6b
esp_hw_support: Add esp_cpu.h abstraction and API
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This commit updates the esp_cpu.h API. The new API presents a new
abstraction of the CPU where CPU presents the following interfaces:
- CPU Control (to stall/unstall/reset the CPU)
- CPU Registers (to read registers commonly used in SW such as SP, PC)
- CPU Interrupts (to inquire/allocate/control the CPUs 32 interrupts)
- Memory Port (to configure the CPU's memory bus for memory protection)
- Debugging (to configure/control the CPU's debugging port)
Note: Also added FORCE_INLINE_ATTR to the DoxyFile in order to pass doc
builds for esp_cpu.h
2022-06-14 14:30:58 +08:00
556ec30457
esp_hw_support: Rename cpu_util.c to cpu.c
2022-06-14 14:30:57 +08:00
03477a59db
rtc_clk: Fix rtc8m calibration failure after cpu/core reset
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1. make sure 8md256 clk is enabled before calibration
2. improve bootloader and application startup 8m, 8md256 enable logic
2022-06-13 17:47:51 +08:00
c8752cee6a
clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem
2022-06-13 17:47:50 +08:00
44f771c713
psram: support s3 copy flash to psram
2022-06-10 10:39:29 +08:00
wuzhenghui