kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feature/support_7.2.8_soc/pvt-dig' into 'master'
rtc: auto adjust LDO voltage based on pvt-dig saved in efuse Closes IDF-4873 See merge request espressif/esp-idf!16365pull/9363/head^2
Michael (XIAO Xufeng)
commit
e7dbfd65cb
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@ -9,7 +9,7 @@
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table 8c7a031bb0def28f2123ac5ee2a48d43
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// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -549,6 +549,26 @@ static const esp_efuse_desc_t SYS_DATA_PART2[] = {
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{EFUSE_BLK10, 0, 256}, // System configuration,
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};
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static const esp_efuse_desc_t K_RTC_LDO[] = {
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{EFUSE_BLK1, 141, 7}, // BLOCK1 K_RTC_LDO,
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};
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static const esp_efuse_desc_t K_DIG_LDO[] = {
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{EFUSE_BLK1, 148, 7}, // BLOCK1 K_DIG_LDO,
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};
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static const esp_efuse_desc_t V_RTC_DBIAS20[] = {
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{EFUSE_BLK1, 155, 8}, // BLOCK1 voltage of rtc dbias20,
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};
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static const esp_efuse_desc_t V_DIG_DBIAS20[] = {
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{EFUSE_BLK1, 163, 8}, // BLOCK1 voltage of digital dbias20,
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};
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static const esp_efuse_desc_t DIG_DBIAS_HVT[] = {
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{EFUSE_BLK1, 171, 5}, // BLOCK1 digital dbias when hvt,
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};
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@ -1218,3 +1238,28 @@ const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
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&SYS_DATA_PART2[0], // System configuration
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = {
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&K_RTC_LDO[0], // BLOCK1 K_RTC_LDO
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = {
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&K_DIG_LDO[0], // BLOCK1 K_DIG_LDO
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = {
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&V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = {
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&V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = {
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&DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt
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NULL
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};
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@ -183,3 +183,11 @@ KEY3, EFUSE_BLK7, 0, 256, Key3 or us
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KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
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KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
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SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
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# AUTO CONFIG DIG&RTC DBIAS#
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################
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K_RTC_LDO, EFUSE_BLK1, 141, 7, BLOCK1 K_RTC_LDO
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K_DIG_LDO, EFUSE_BLK1, 148, 7, BLOCK1 K_DIG_LDO
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V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20
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V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, BLOCK1 voltage of digital dbias20
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DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, BLOCK1 digital dbias when hvt
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Nie można renderować tego pliku, ponieważ zawiera nieoczekiwany znak w wierszu 8 i kolumnie 53.
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@ -10,7 +10,7 @@ extern "C" {
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#include "esp_efuse.h"
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// md5_digest_table 8c7a031bb0def28f2123ac5ee2a48d43
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// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -149,6 +149,11 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
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extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
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extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
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extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
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extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
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extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
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extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
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extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
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#ifdef __cplusplus
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}
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@ -30,10 +30,15 @@ static uint32_t s_cur_pll_freq;
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static uint32_t s_apb_freq;
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static void rtc_clk_cpu_freq_to_xtal(int freq, int div);
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void rtc_clk_cpu_freq_to_xtal(int freq, int div);
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static void rtc_clk_cpu_freq_to_8m(void);
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static bool rtc_clk_set_bbpll_always_on(void);
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extern uint32_t g_dig_dbias_pvt_240m;
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extern uint32_t g_rtc_dbias_pvt_240m;
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extern uint32_t g_dig_dbias_pvt_non_240m;
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extern uint32_t g_rtc_dbias_pvt_non_240m;
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void rtc_clk_32k_enable(bool enable)
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{
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if (enable) {
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@ -94,18 +99,6 @@ bool rtc_clk_8md256_enabled(void)
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return clk_ll_rc_fast_d256_is_enabled();
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}
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static void wait_dig_dbias_valid(uint64_t rtc_cycles)
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{
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soc_rtc_slow_clk_src_t slow_clk_freq = rtc_clk_slow_src_get();
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rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
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if (slow_clk_freq == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
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cal_clk = RTC_CAL_32K_XTAL;
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} else if (slow_clk_freq == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
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cal_clk = RTC_CAL_8MD256;
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}
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rtc_clk_cal(cal_clk, rtc_cycles);
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}
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void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
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{
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clk_ll_rtc_slow_set_src(clk_src);
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@ -182,17 +175,45 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
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*/
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static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
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{
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int dbias = (cpu_freq_mhz == 240) ? DIG_DBIAS_240M : DIG_DBIAS_80M_160M;
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, dbias);
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wait_dig_dbias_valid(2);
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/* cpu_frequency < 240M: dbias = pvt-dig + 2;
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cpu_frequency = 240M: dbias = pvt-dig + 3;
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*/
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if (cpu_freq_mhz != 240) {
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
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} else {
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_240m);
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}
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esp_rom_delay_us(40);
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clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz);
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clk_ll_cpu_set_divider(1);
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/* switch clock source */
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
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rtc_clk_apb_freq_update(80 * MHZ);
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ets_update_cpu_frequency(cpu_freq_mhz);
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/* There are totally 6 LDO slaves(all on by default). At the moment of swithing LDO slave, LDO voltage will also change instantaneously.
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* LDO slave can reduce the voltage change caused by switching frequency.
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* CPU frequency <= 40M : just open 3 LDO slaves; CPU frequency = 80M : open 4 LDO slaves; CPU frequency = 160M : open 5 LDO slaves; CPU frequency = 240M : open 6 LDO slaves;
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*
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* LDO voltage will decrease at the moment of switching from low frequency to high frequency; otherwise, LDO voltage will increase.
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* In order to reduce LDO voltage drop, LDO voltage should rise first then fall.
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*/
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int pd_slave = cpu_freq_mhz / 80;
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rtc_cpu_freq_config_t cur_config;
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rtc_clk_cpu_freq_get_config(&cur_config);
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if (cpu_freq_mhz > cur_config.freq_mhz) {
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REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE >> pd_slave);
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clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz);
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clk_ll_cpu_set_divider(1);
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/* switch clock source */
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
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rtc_clk_apb_freq_update(80 * MHZ);
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ets_update_cpu_frequency(cpu_freq_mhz);
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} else {
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clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz);
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clk_ll_cpu_set_divider(1);
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/* switch clock source */
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
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rtc_clk_apb_freq_update(80 * MHZ);
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ets_update_cpu_frequency(cpu_freq_mhz);
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REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE >> pd_slave);
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}
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}
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bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
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@ -336,30 +357,33 @@ void rtc_clk_cpu_freq_set_xtal(void)
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/**
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* Switch to XTAL frequency. Does not disable the PLL.
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* Public function for testing only.
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*/
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static void rtc_clk_cpu_freq_to_xtal(int freq, int div)
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void rtc_clk_cpu_freq_to_xtal(int freq, int div)
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{
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
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esp_rom_delay_us(40);
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ets_update_cpu_frequency(freq);
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/* set digital voltage for different cpu freq from xtal */
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int dbias = (freq <= 2) ? DIG_DBIAS_2M : DIG_DBIAS_XTAL;
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias);
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wait_dig_dbias_valid(2);
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/* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */
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clk_ll_cpu_set_divider(1);
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clk_ll_cpu_set_divider(div);
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/* switch clock source */
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
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rtc_clk_apb_freq_update(freq * MHZ);
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REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE);
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}
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static void rtc_clk_cpu_freq_to_8m(void)
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{
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ets_update_cpu_frequency(20);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL);
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wait_dig_dbias_valid(2);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
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esp_rom_delay_us(40);
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clk_ll_cpu_set_divider(1);
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
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rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX);
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REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE);
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}
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rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
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@ -24,7 +24,7 @@
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#include "esp_efuse.h"
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#include "esp_efuse_table.h"
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#include "esp_private/spi_flash_os.h"
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#include "hal/efuse_hal.h"
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#define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
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@ -32,6 +32,13 @@ static const char *TAG = "rtcinit";
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static void set_ocode_by_efuse(int calib_version);
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static void calibrate_ocode(void);
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static void rtc_set_stored_dbias(void);
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// Initial values are used for bootloader, and these variables will be re-assigned based on efuse values during application startup
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uint32_t g_dig_dbias_pvt_240m = 28;
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uint32_t g_rtc_dbias_pvt_240m = 28;
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uint32_t g_dig_dbias_pvt_non_240m = 27;
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uint32_t g_rtc_dbias_pvt_non_240m = 27;
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void rtc_init(rtc_config_t cfg)
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{
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@ -89,6 +96,12 @@ void rtc_init(rtc_config_t cfg)
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}
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}
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//LDO dbias initialization
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rtc_set_stored_dbias();
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
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if (cfg.clkctl_init) {
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//clear CMMU clock force on
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CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON);
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@ -301,3 +314,116 @@ static void calibrate_ocode(void)
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spi_timing_change_speed_mode_cache_safe(false);
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#endif
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}
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static uint32_t get_dig_dbias_by_efuse(uint8_t pvt_scheme_ver)
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{
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assert(pvt_scheme_ver == 1);
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uint32_t dig_dbias = 28;
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esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, ESP_EFUSE_DIG_DBIAS_HVT[0]->bit_count);
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if (err != ESP_OK) {
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dig_dbias = 28;
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ESP_HW_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias);
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}
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return dig_dbias;
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}
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static uint32_t get_rtc_dbias_by_efuse(uint8_t pvt_scheme_ver, uint32_t dig_dbias)
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{
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assert(pvt_scheme_ver == 1);
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uint32_t rtc_dbias = 0;
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signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0;
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esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, ESP_EFUSE_K_RTC_LDO[0]->bit_count);
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esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, ESP_EFUSE_K_DIG_LDO[0]->bit_count);
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esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, ESP_EFUSE_V_RTC_DBIAS20[0]->bit_count);
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esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, ESP_EFUSE_V_DIG_DBIAS20[0]->bit_count);
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if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) {
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k_rtc_ldo = 0;
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k_dig_ldo = 0;
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v_rtc_bias20 = 0;
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v_dig_bias20 = 0;
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ESP_HW_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20);
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}
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k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): (uint8_t)k_rtc_ldo;
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k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
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v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20;
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v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
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uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500;
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uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
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signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo;
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signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
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uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
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for (rtc_dbias = 15; rtc_dbias < 31; rtc_dbias++) {
|
||||
uint32_t v_rtc_nearest_1v15_mul10000 = 0;
|
||||
v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20);
|
||||
if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
return rtc_dbias;
|
||||
}
|
||||
|
||||
static uint32_t get_dig1v3_dbias_by_efuse(uint8_t pvt_scheme_ver)
|
||||
{
|
||||
assert(pvt_scheme_ver == 1);
|
||||
signed int k_dig_ldo = 0, v_dig_bias20 = 0;
|
||||
esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, ESP_EFUSE_K_DIG_LDO[0]->bit_count);
|
||||
esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, ESP_EFUSE_V_DIG_DBIAS20[0]->bit_count);
|
||||
if ((err0 != ESP_OK) | (err1 != ESP_OK)) {
|
||||
k_dig_ldo = 0;
|
||||
v_dig_bias20 = 0;
|
||||
ESP_HW_LOGW(TAG, "efuse read fail, k_dig_ldo: %d, v_dig_bias20: %d\n", k_dig_ldo, v_dig_bias20);
|
||||
}
|
||||
|
||||
k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
|
||||
v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
|
||||
|
||||
uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
|
||||
signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
|
||||
uint32_t dig_dbias =15;
|
||||
for (dig_dbias = 15; dig_dbias < 31; dig_dbias++) {
|
||||
uint32_t v_dig_nearest_1v3_mul10000 = 0;
|
||||
v_dig_nearest_1v3_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
|
||||
if (v_dig_nearest_1v3_mul10000 >= 13000) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
return dig_dbias;
|
||||
}
|
||||
|
||||
static void rtc_set_stored_dbias(void)
|
||||
{
|
||||
/*
|
||||
1. a reasonable dig_dbias which by scaning pvt to make 240 CPU run successful stored in efuse;
|
||||
2. also we store some value in efuse, include:
|
||||
k_rtc_ldo (slope of rtc voltage & rtc_dbias);
|
||||
k_dig_ldo (slope of digital voltage & digital_dbias);
|
||||
v_rtc_bias20 (rtc voltage when rtc dbais is 20);
|
||||
v_dig_bias20 (digital voltage when digital dbais is 20).
|
||||
3. a reasonable rtc_dbias can be calculated by a certion formula.
|
||||
4. save these values for reuse
|
||||
*/
|
||||
uint8_t blk_minor = efuse_ll_get_blk_version_minor();
|
||||
uint8_t blk_major = efuse_ll_get_blk_version_major();
|
||||
uint8_t pvt_scheme_ver = 0;
|
||||
if ( (blk_major <= 1 && blk_minor == 1) || blk_major > 1 || (blk_major == 1 && blk_minor >= 2) ) {
|
||||
/* PVT supported after blk_ver 1.2 */
|
||||
pvt_scheme_ver = 1;
|
||||
}
|
||||
|
||||
if (pvt_scheme_ver == 1) {
|
||||
uint32_t dig1v3_dbias = get_dig1v3_dbias_by_efuse(pvt_scheme_ver);
|
||||
uint32_t dig_dbias = get_dig_dbias_by_efuse(pvt_scheme_ver);
|
||||
if (dig_dbias != 0) {
|
||||
g_dig_dbias_pvt_240m = MIN(dig1v3_dbias, dig_dbias + 3);
|
||||
g_dig_dbias_pvt_non_240m = MIN(dig1v3_dbias, dig_dbias + 2);
|
||||
g_rtc_dbias_pvt_240m = get_rtc_dbias_by_efuse(pvt_scheme_ver, g_dig_dbias_pvt_240m);
|
||||
g_rtc_dbias_pvt_non_240m = get_rtc_dbias_by_efuse(pvt_scheme_ver, g_dig_dbias_pvt_non_240m);
|
||||
} else {
|
||||
ESP_HW_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in blk version: 0%d\n", pvt_scheme_ver);
|
||||
}
|
||||
} else {
|
||||
ESP_HW_LOGD(TAG, "core voltage not decided in efuse, use default value.");
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -126,6 +126,22 @@ set sleep_init default param
|
|||
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 0xf
|
||||
|
||||
|
||||
/*
|
||||
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
|
||||
storing in efuse
|
||||
*/
|
||||
#define K_RTC_MID_MUL10000 198
|
||||
#define K_DIG_MID_MUL10000 211
|
||||
#define V_RTC_MID_MUL10000 10181
|
||||
#define V_DIG_MID_MUL10000 10841
|
||||
|
||||
/*
|
||||
set LDO slave during CPU switch
|
||||
*/
|
||||
#define DEFAULT_LDO_SLAVE 0x7
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -3683,6 +3683,9 @@ ork.*/
|
|||
#define RTC_CNTL_DISABLE_RTC_CPU_V 0x1
|
||||
#define RTC_CNTL_DISABLE_RTC_CPU_S 31
|
||||
|
||||
/*
|
||||
Due to the LDO slaves, RTC_CNTL_DATE_REG[18:13] can only be used for LDO adjustment.
|
||||
*/
|
||||
#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x1FC)
|
||||
/* RTC_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101271 ; */
|
||||
/*description: .*/
|
||||
|
|
@ -3690,7 +3693,12 @@ ork.*/
|
|||
#define RTC_CNTL_DATE_M ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S))
|
||||
#define RTC_CNTL_DATE_V 0xFFFFFFF
|
||||
#define RTC_CNTL_DATE_S 0
|
||||
|
||||
/*LDO SLAVE : R/W ;bitpos:[18:13] ; default: 6'd0 ;*/
|
||||
/*description: .*/
|
||||
#define RTC_CNTL_SLAVE_PD 0x0000003F
|
||||
#define RTC_CNTL_SLAVE_PD_M ((RTC_CNTL_SLAVE_V)<<(RTC_CNTL_SLAVE_S))
|
||||
#define RTC_CNTL_SLAVE_PD_V 0x3F
|
||||
#define RTC_CNTL_SLAVE_PD_S 13
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue