David Banks
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ae88d35ce7
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CPLD: final pinout changes
Change-Id: I8b18f9f4b3445a79b82b5667971725cb8636fe9a
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2018-06-12 12:39:06 +01:00 |
David Banks
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d49c1896fb
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CPLD: Juggled GPIO assignments so CPLD pin 33 (GSR) connects to GPIO18 (Version)
Change-Id: I6ea4e6ad40d7eb4f785df31ae14a446e05a0be46
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2018-06-12 10:22:29 +01:00 |
David Banks
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c595278204
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CPLD: Added version support to both CPLDs
Change-Id: Ie2b0698a4ba523b392507349a37a6554daafbc0b
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2018-06-09 13:24:47 +01:00 |
David Banks
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7396747665
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CPLD and Pi Firmware: Revert to Quad starting at GPIO2
Change-Id: I1a9eeb28150b83e2183c516643d7d65330783697
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2018-06-09 11:32:03 +01:00 |
David Banks
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9f37dafa12
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CPLD: Added global buffer for sp_clk
Change-Id: Id572c9e95d166311e7d46512da9fa45a05c1131d
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2018-06-08 20:39:29 +01:00 |
David Banks
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5cf77dc03c
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CPLD: Updated pinout to quad starts at gpio0, sp_clken now a global input
Change-Id: Ie8ed78de07dce868f644041806361f73b575a403
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2018-06-08 07:35:27 +01:00 |
David Banks
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ba112a6aad
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CPLD: Added spare (gpio0) and sp_clken (gpio1)
Change-Id: I74b1af2fe1b51e5e15645b8758ea2a9952649c2c
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2018-06-06 17:51:11 +01:00 |
David Banks
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a92cb3d43f
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CPLD and Pi Firmware: swapped gpio assignments for gpio20 and gpio23 (sp_clk and sp_data) as prototype had noise spikes on gpio20
Change-Id: Ibb2dc20c738e499dc106d61fec516b8fc35bdf73
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2018-06-06 14:39:02 +01:00 |
David Banks
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76e055d293
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CPLD: Removed SW1Out passthrough to save a product term
Change-Id: Ib22720e83a89e11233093768de3c1f4ca5b60017
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2018-06-06 14:28:12 +01:00 |
David Banks
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88a183e3ee
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KiCad and CPLD: final small changes to bring SW2/3/link inputs and LED1 output to CPLD (unused)
Change-Id: I054dcab88885547d6ceb07bc2759daf81372ef52
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2018-06-05 18:58:11 +01:00 |
David Banks
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65b90f2ba4
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CPLD: Updated to pinout from PCB based design
Change-Id: Ia13272589b9886c587bef7645dd2ee0809ac1e7f
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2018-06-05 17:52:51 +01:00 |
David Banks
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2dc99dccaa
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Added support for manual calibration button
Change-Id: I00867668c208bea174b88650ac8fc25d7767c3ed
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2017-05-28 12:09:58 +01:00 |
David Banks
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e7675e9fa8
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Fix counter pipelining issue
Change-Id: I66584fbf2dfb375dd7e77b5f4a214224b2552519
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2017-05-25 19:31:43 +01:00 |
David Banks
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082f772e55
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Moved to 6 sampling points in Mode 7
Change-Id: I888d9911fe6be96f48bf9429650b4a13ae3c185d
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2017-05-25 17:23:49 +01:00 |
David Banks
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81720e677c
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Route SW through CPLD to Pi
Change-Id: I467e7a5b4df797d0770dce132d007cfe2c63234f
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2017-05-25 15:12:09 +01:00 |
David Banks
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70d559303d
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Make sampling points soft-programmable by the Pi
Change-Id: I42a1a73e084779106953d019809e4be943c76ead
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2017-05-24 13:20:06 +01:00 |
David Banks
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00e555bfdf
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Automatic mode 7 support
Change-Id: I93568cd3822e7e5aed9ff8b61d62eaa8a4fda193
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2017-04-26 22:19:41 +01:00 |
David Banks
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6d0263f280
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Removed obsolete VSYNC logic from CPLD, pass through CSYNC to ARM
Change-Id: I01c855dfd71e225bafbc5a03841581e9ff5c33cb
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2017-04-26 18:15:47 +01:00 |
David Banks
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123ae936e1
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Set all outputs to SLOW to reduce noise
Change-Id: I8d28858c0972310a24c561575e341613278cfaa7
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2017-04-25 12:55:20 +01:00 |
David Banks
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7fa14552bd
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Initial version of VHDL
Change-Id: I2fbdf73bc0feb8955a2b4b70856203e370cbad30
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2017-04-24 20:21:18 +01:00 |