19 Commity (a2ec8cce30542df7c85b905bc0a20ae904937809)

Autor	SHA1	Wiadomość	Data
IanSB	c2d17bfe94	CPLD V6.4 separate vsync	2019-04-03 20:32:22 +01:00
IanSB	01ccdbded8	Binary .jed for CPLD v6.3	2019-03-31 16:26:40 +01:00
David Banks	6778315345	CPLD: Fixed a bug with half-pixel delay (now v6.2) ... Change-Id: I110ba7cb322438801aa26ce51a933a1d7d40804c	2019-03-24 12:11:12 +00:00
David Banks	58fb277106	CPLD: Increased counter from 7 back to 8 bits (now v6.1) ... Change-Id: Ia803625db0b88204f41de3f81ba5d870d1ea1e40	2019-03-24 08:42:36 +00:00
David Banks	989d098b32	Delay reduced to 2 bits plus psync changes (now v6.0) ... Change-Id: Ie84ecd1556d796a8edd9080d14ec0e8acbefdd16	2019-03-23 18:33:53 +00:00
David Banks	a2d5ed5722	CPLD: Added sync invert function (now v5.0) ... Change-Id: Ie1701c5ba25e198e741cb51ce87b33e708b415f1	2019-03-14 18:10:30 +00:00
David Banks	a03b884f3e	CPLD: Reverted: Align quad timing back to cycle 0 as before (issues at offset 0) ... Change-Id: I83aa6f555695a1cd5a607e676a4b110cfdbf35e9	2019-03-13 13:57:51 +00:00
David Banks	ecc5813441	CPLD: Fix long-standing bug concerning offset selection in Mode 0..6 ... Change-Id: I463f8d8994c365bbbb8d6d8c1ff2804401fc3380	2019-03-12 22:42:09 +00:00
David Banks	a58cd27837	CPLD: Optimize generation of PSync, and allow more skew ... Change-Id: Id63a46a5cd909fd22445573666010a635e24a433	2019-03-12 21:31:11 +00:00
David Banks	b4f808ee0d	CPLD: Added half-odd and half-even sampling (now v4.0) ... Change-Id: Ie349def5dacf1fe73cc15199c3cf4607e2332e7a	2019-03-12 18:47:29 +00:00
David Banks	8a21efe080	CPLD: Re-order bits when rate=1 ... Change-Id: Iee51a1916c47d95d4683578836f4c1b6f531e8b8	2019-03-08 13:49:25 +00:00
David Banks	30d1cec731	Implement rate bit to support double rate (6 bits/pixel) sampling ... Change-Id: I324b9ea804f449e208361071d5081d28f9acf85d	2019-03-08 11:39:57 +00:00
David Banks	d5a13e0077	CPLD: Updated fitting notes and .jed file with v2.3 ... Change-Id: I7a258df7f5f8b9610f8ef24242fbec24ec2f11ec	2019-03-08 11:14:59 +00:00
David Banks	17b6673b13	CPLD: Correct issue with delay in 6 clocks/pixel mode ... Change-Id: I55c2e8bf34a31d5fcbc2559d9ebc7af7257a71ec	2019-02-25 19:57:29 +00:00
David Banks	cb5a8461b6	CPLD: Start sampling 8us earlier ... Change-Id: I0f1215f801f46472597130476e8912a25bf00e38	2018-11-11 17:20:58 +00:00
David Banks	035381c1fc	CPLD: Increment to version 2.0 and update checked-in .jed file ... Change-Id: I58fe111c1bf969abe7692cffacd7d20a73647df6	2018-10-29 15:27:31 +00:00
David Banks	5d7839ec84	CPLD: Re-centred MODE 7 screen ... Change-Id: I70d8d27c773cddb849985c7ead85a71faaf8ed8b	2018-10-25 11:01:36 +01:00
David Banks	a546d6bd42	CPLD: Updated released .jed file to v1.1 ... Change-Id: I2bdeddc68e3e3606425bae5d779a8db7729a8dac	2018-10-16 15:53:52 +01:00
David Banks	54bba7c5e1	Added JEDEC file for the 1.0 release ... Change-Id: I78e6c0897c3825954e9a9a5ec4b9b676323d24eb	2018-09-23 12:38:00 +01:00