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RGBtoHDMI
kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
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1 285 Commity
17 Gałęzie
93 Tagi
20 MiB
Wykres commitów

1285 Commity (9700c58e5289179370926f9d7fca79f27e098cf7)

Autor SHA1 Wiadomość Data
David Banks 127c804a5e Extended clock calibration to correctly handle 624-line non-interlaced modes 
Change-Id: I6aaf957512e0f9d77df89d835f8cf40b4d801506
 2017-04-30 12:55:40 +01:00
David Banks 4cf99c2a91 Overscan horizontally by 32 pixels 
Change-Id: Ib4dec873d22a89e4f6463fc0aaa18e7f0952b661
 2017-04-30 12:19:10 +01:00
David Banks 933728c9d3 Only show grey background in DEBUG mode 
Change-Id: I96ba90ca3fa9924b28c534af81f9513c5180880b
 2017-04-30 12:18:07 +01:00
David Banks 5d2c60e23b Improve handling of non-interlaced mode by line doubling 
Change-Id: I90ec9457dbf2974b67f666144bf3d11e5bda82bb
 2017-04-30 11:51:51 +01:00
David Banks e0e2d3bfdb Changed some log_info to log_debug 
Change-Id: I11d52619675c5bff86fdeb9c4977bd19c5ec7081
 2017-04-30 10:58:03 +01:00
David Banks d54fba890a Made accesses to clock registers volatile 
Change-Id: Ieb21bf648ea2c3a52b644a597225a93fd7b32ad8
 2017-04-30 10:57:06 +01:00
David Banks 8b0cb940f8 Deleted unused build files 
Change-Id: I3b2a8a327f8509dc2955a2fff038db0266ceaee3
 2017-04-30 10:56:02 +01:00
David Banks dac270bc4d Freed up a couple of registers 
Change-Id: Ic25ce5edb5dd476db55042711afeed781ec83db5
 2017-04-30 10:42:35 +01:00
David Banks 6473d100ee Clear screen on entry 
Change-Id: Id9eeeb4d12c6daab9f14834eed7c1e145c0150c1
 2017-04-27 21:25:40 +01:00
David Banks c169996467 Calibrate clock based on VSYNC time 
Change-Id: I39dab208f2af217662921ffca6f5f8f69c7d6edb
 2017-04-27 15:27:26 +01:00
David Banks 00e555bfdf Automatic mode 7 support 
Change-Id: I93568cd3822e7e5aed9ff8b61d62eaa8a4fda193
 2017-04-26 22:19:41 +01:00
David Banks 6d0263f280 Removed obsolete VSYNC logic from CPLD, pass through CSYNC to ARM 
Change-Id: I01c855dfd71e225bafbc5a03841581e9ff5c33cb
 2017-04-26 18:15:47 +01:00
David Banks 1bf8ebb272 Switch to software processing of CSYNC to find VSYNC and Odd/Even field 
Change-Id: Ied519b072e75da67559f5e867b012c7b5ae74eb1
 2017-04-26 17:49:23 +01:00
David Banks 4335d4e531 Early work on Mode 7 
Change-Id: I0cea302fd7ea9ea8cb3649721185c2351b7084dc
 2017-04-25 18:24:49 +01:00
David Banks b9fc578bff Added a LINE_DOUBLE #define 
Change-Id: I0c385d6bca14e9a163ce927927acc34a021635dc
 2017-04-25 15:37:41 +01:00
David Banks c9f4d27c1e Set core_freq to 383.9MHz via mailbox 
Change-Id: Ic9cc77ecc94bac17e242a9bbab4581a496515086
 2017-04-25 15:14:01 +01:00
David Banks 2934293d99 Improve noise immunity of psync and hsync edge detection - make a big difference! 
Change-Id: I4e13402a1f430a20804ed46e4f9d3bb9b9b30860
 2017-04-25 14:48:43 +01:00
David Banks a0b2817ab1 Tweak sampling position by one notch 
Change-Id: I4dfdb5c424b584596b2beabb5df0e86e4ba393eb
 2017-04-25 12:55:47 +01:00
David Banks 123ae936e1 Set all outputs to SLOW to reduce noise 
Change-Id: I8d28858c0972310a24c561575e341613278cfaa7
 2017-04-25 12:55:20 +01:00
David Banks d11647e620 Added some noise immunity to vsync 
Change-Id: I7a678fdab841f009742ed2f9857f7d1b83515b45
 2017-04-25 12:05:50 +01:00
David Banks cf17594877 Implemented vsync 
Change-Id: I35d7dc7a0184e147faa64fadf038752e7df467b9
 2017-04-25 11:53:22 +01:00
David Banks 29d99e7110 VHDL: Adjust count when quad loaded 
Change-Id: Ieaf096aa6ffb574e470564ca70602ee92bde57ce
 2017-04-25 10:06:38 +01:00
David Banks 6c519cdc29 VHDL: idle psync should be zero 
Change-Id: I3422fb75376be0c3a29e8f02b5019910e9c84614
 2017-04-25 09:57:21 +01:00
David Banks 140b89d311 VHDL: Increased counter to 11 bits 
Change-Id: I269a63881ae52115f5989f72e85a536ed79f7e2f
 2017-04-25 09:53:15 +01:00
David Banks e3dbea5b30 VHDL: Updated .xise file 
Change-Id: I8d8fdbac96ed32383779f61b69c88800ee6bfcf9
 2017-04-25 09:52:49 +01:00
David Banks 27822940d2 Make virtual frame buffer same size as physical frame buffer 
Change-Id: Iba681af707024e891232e455dd7a6575bf4af845
 2017-04-25 09:37:26 +01:00
David Banks 0ba2591092 Switch to 1920x1080 
Change-Id: I33c8be2ff723ccf8798eb72ad9193d8c4b383ac1
 2017-04-25 09:35:30 +01:00
David Banks 84935e5f61 Update core clock to 384MHz, add hdmi settings 
Change-Id: I6b65f69cab9ed775ba2b0a1363ae2d15cc8b5656
 2017-04-25 07:17:49 +01:00
David Banks f4a2b1c8bf Skip alternate lines to maintain aspect ratio 
Change-Id: If1112e7b0af8107d88d9709f18e9a9df546a5ea0
 2017-04-25 07:17:07 +01:00
David Banks 3ab2faf6e4 Add a grey background to framebuffer for debugging 
Change-Id: Ifafe6f724d5294f7920dae5ecda6cbbc03a869ad
 2017-04-25 07:01:39 +01:00
David Banks cbb5e4d1b8 Fix pixel misordering within byte 
Change-Id: I82a20a49b4004dbbb25986a4fce59ea84f197a17
 2017-04-25 07:00:50 +01:00
David Banks 2c547292fa Added code to copy RGB to framebuffer 
Change-Id: Id738bdab509091155d4aeff5cf652ca4334e93a6
 2017-04-24 22:34:39 +01:00
David Banks 53088a5360 Added .gitignore 
Change-Id: I0d9fc178a6827186b7e1feed4050014816187f21
 2017-04-24 20:29:19 +01:00
David Banks 4de2a629a0 Initial version of RGBtoHTML 
Change-Id: Ie4c692e283bbdaaa7d2e093ec23fb83ee6b7b4af
 2017-04-24 20:29:02 +01:00
David Banks 7fa14552bd Initial version of VHDL 
Change-Id: I2fbdf73bc0feb8955a2b4b70856203e370cbad30
 2017-04-24 20:21:18 +01:00