2003-06-22 19:36:37 +00:00
|
|
|
/*
|
|
|
|
* Hamlib Rotator backend - SDR-1000
|
2004-02-08 17:41:52 +00:00
|
|
|
* Copyright (c) 2003-2004 by Stephane Fillod
|
2003-06-22 19:36:37 +00:00
|
|
|
*
|
2004-10-02 20:37:24 +00:00
|
|
|
* $Id: sdr1k.c,v 1.7 2004-10-02 20:37:24 fillods Exp $
|
2003-06-22 19:36:37 +00:00
|
|
|
*
|
|
|
|
* This library is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU Library General Public License as
|
|
|
|
* published by the Free Software Foundation; either version 2 of
|
|
|
|
* the License, or (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU Library General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU Library General Public
|
|
|
|
* License along with this library; if not, write to the Free Software
|
|
|
|
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifdef HAVE_CONFIG_H
|
|
|
|
#include "config.h"
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#include <stdlib.h>
|
|
|
|
#include <string.h> /* String function definitions */
|
|
|
|
#include <unistd.h> /* UNIX standard function definitions */
|
2003-10-07 22:21:57 +00:00
|
|
|
#include <math.h>
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
#include "hamlib/rig.h"
|
2004-10-02 20:37:24 +00:00
|
|
|
#include "parallel.h"
|
2003-06-22 19:36:37 +00:00
|
|
|
#include "misc.h"
|
|
|
|
#include "bandplan.h"
|
|
|
|
#include "register.h"
|
|
|
|
|
|
|
|
#include "sdr1k.h"
|
|
|
|
|
|
|
|
static int sdr1k_set_freq(RIG *rig, vfo_t vfo, freq_t freq);
|
|
|
|
static int sdr1k_get_freq(RIG *rig, vfo_t vfo, freq_t *freq);
|
|
|
|
static int sdr1k_reset(RIG *rig, reset_t reset);
|
|
|
|
static int sdr1k_init(RIG *rig);
|
|
|
|
static int sdr1k_open(RIG *rig);
|
|
|
|
static int sdr1k_close(RIG *rig);
|
|
|
|
static int sdr1k_cleanup(RIG *rig);
|
|
|
|
static int sdr1k_set_ptt (RIG *rig, vfo_t vfo, ptt_t ptt);
|
2003-11-16 17:22:06 +00:00
|
|
|
static int sdr1k_set_level (RIG *rig, vfo_t vfo, setting_t level, value_t val);
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
typedef enum { L_EXT = 0, L_BAND = 1, L_DDS0 = 2, L_DDS1 = 3 } latch_t;
|
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
#define TR 0x40
|
|
|
|
#define MUTE 0x80
|
|
|
|
#define GAIN 0x80
|
|
|
|
#define WRB 0x40
|
|
|
|
#define RESET 0x80
|
|
|
|
|
|
|
|
/* DDS Control Constants */
|
|
|
|
#define COMP_PD 0x10 /* DDS Comparator power down */
|
|
|
|
#define DIG_PD 0x01 /* DDS Digital Power down */
|
|
|
|
#define BYPASS_PLL 0x20 /* Bypass DDS PLL */
|
|
|
|
#define INT_IOUD 0x01 /* Internal IO Update */
|
|
|
|
#define OSK_EN 0x20 /* Offset Shift Keying enable */
|
|
|
|
#define OSK_INT 0x10 /* Offset Shift Keying */
|
|
|
|
#define BYPASS_SINC 0x40 /* Bypass Inverse Sinc Filter */
|
|
|
|
#define PLL_RANGE 0x40 /* Set PLL Range */
|
|
|
|
|
|
|
|
static int write_latch (RIG *rig, latch_t which, unsigned value, unsigned mask);
|
|
|
|
static int dds_write_reg (RIG *rig, unsigned addr, unsigned data);
|
|
|
|
static int set_bit (RIG *rig, latch_t reg, unsigned bit, unsigned state);
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
|
2003-09-28 15:36:57 +00:00
|
|
|
#define DEFAULT_XTAL MHz(200)
|
2003-10-07 22:21:57 +00:00
|
|
|
#define DEFAULT_PLL_MULT 1
|
|
|
|
#define DEFAULT_DAC_MULT 4095
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
struct sdr1k_priv_data {
|
2003-10-07 22:21:57 +00:00
|
|
|
unsigned shadow[4]; /* shadow latches */
|
|
|
|
freq_t dds_freq; /* current freq */
|
2003-09-28 15:36:57 +00:00
|
|
|
freq_t xtal; /* base XTAL */
|
2003-10-07 22:21:57 +00:00
|
|
|
int pll_mult; /* PLL mult */
|
2003-06-22 19:36:37 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
2003-09-28 15:36:57 +00:00
|
|
|
#define SDR1K_FUNC RIG_FUNC_MUTE
|
|
|
|
#define SDR1K_LEVEL RIG_LEVEL_PREAMP
|
2003-06-22 19:36:37 +00:00
|
|
|
#define SDR1K_PARM RIG_PARM_NONE
|
|
|
|
|
|
|
|
#define SDR1K_MODES (RIG_MODE_NONE)
|
|
|
|
|
|
|
|
#define SDR1K_VFO RIG_VFO_A
|
|
|
|
|
|
|
|
#define SDR1K_ANTS 0
|
|
|
|
|
|
|
|
|
|
|
|
/* ************************************************************************* */
|
|
|
|
/*
|
|
|
|
* http://www.flex-radio.com
|
|
|
|
* SDR-1000 rig capabilities.
|
|
|
|
*
|
|
|
|
*
|
2003-11-16 17:22:06 +00:00
|
|
|
* TODO: RIG_FUNC_MUTE, set_external_pin?
|
2003-06-22 19:36:37 +00:00
|
|
|
*
|
|
|
|
* def set_mute (self, mute = 1):
|
|
|
|
* self.set_bit(1, 7, mute)
|
|
|
|
*
|
|
|
|
* def set_unmute (self):
|
|
|
|
* self.set_bit(1, 7, 0)
|
|
|
|
*
|
|
|
|
* def set_external_pin (self, pin, on = 1):
|
|
|
|
* assert (pin < 8 and pin > 0), "Out of range 1..7"
|
|
|
|
* self.set_bit(0, pin-1, on)
|
2003-09-28 15:36:57 +00:00
|
|
|
*
|
2003-10-07 22:21:57 +00:00
|
|
|
* def read_input_pin
|
|
|
|
*
|
|
|
|
* set_conf(XTAL,PLL_mult,spur_red)
|
|
|
|
*
|
|
|
|
* What about IOUD_Clock?
|
2003-06-22 19:36:37 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
const struct rig_caps sdr1k_rig_caps = {
|
|
|
|
.rig_model = RIG_MODEL_SDR1000,
|
|
|
|
.model_name = "SDR-1000",
|
|
|
|
.mfg_name = "Flex-radio",
|
2003-10-07 22:21:57 +00:00
|
|
|
.version = "0.1.2",
|
2003-06-22 19:36:37 +00:00
|
|
|
.copyright = "LGPL",
|
|
|
|
.status = RIG_STATUS_NEW,
|
|
|
|
.rig_type = RIG_TYPE_TUNER,
|
|
|
|
.targetable_vfo = 0,
|
|
|
|
.ptt_type = RIG_PTT_RIG,
|
|
|
|
.dcd_type = RIG_DCD_NONE,
|
|
|
|
.port_type = RIG_PORT_PARALLEL,
|
|
|
|
|
|
|
|
.has_get_func = SDR1K_FUNC,
|
|
|
|
.has_set_func = SDR1K_FUNC,
|
|
|
|
.has_get_level = SDR1K_LEVEL,
|
|
|
|
.has_set_level = RIG_LEVEL_SET(SDR1K_LEVEL),
|
|
|
|
.has_get_parm = SDR1K_PARM,
|
|
|
|
.has_set_parm = RIG_PARM_SET(SDR1K_PARM),
|
|
|
|
.chan_list = {
|
|
|
|
RIG_CHAN_END,
|
|
|
|
},
|
|
|
|
.scan_ops = RIG_SCAN_NONE,
|
|
|
|
.vfo_ops = RIG_OP_NONE,
|
|
|
|
.transceive = RIG_TRN_OFF,
|
|
|
|
.attenuator = { RIG_DBLST_END, },
|
2003-10-07 22:21:57 +00:00
|
|
|
.preamp = { 14, RIG_DBLST_END, },
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
.rx_range_list1 = { {.start=Hz(1),.end=MHz(65),.modes=SDR1K_MODES,
|
|
|
|
.low_power=-1,.high_power=-1,SDR1K_VFO},
|
|
|
|
RIG_FRNG_END, },
|
|
|
|
.tx_range_list1 = {
|
|
|
|
/* restricted to ham band */
|
|
|
|
FRQ_RNG_HF(1,SDR1K_MODES, W(1),W(1),SDR1K_VFO,SDR1K_ANTS),
|
|
|
|
FRQ_RNG_6m(1,SDR1K_MODES, W(1),W(1),SDR1K_VFO,SDR1K_ANTS),
|
|
|
|
RIG_FRNG_END, },
|
|
|
|
|
|
|
|
.rx_range_list2 = { {.start=Hz(1),.end=MHz(65),.modes=SDR1K_MODES,
|
|
|
|
.low_power=-1,.high_power=-1,SDR1K_VFO},
|
|
|
|
RIG_FRNG_END, },
|
|
|
|
.tx_range_list2 = {
|
|
|
|
/* restricted to ham band */
|
|
|
|
FRQ_RNG_HF(2,SDR1K_MODES, W(1),W(1),SDR1K_VFO,SDR1K_ANTS),
|
|
|
|
FRQ_RNG_6m(2,SDR1K_MODES, W(1),W(1),SDR1K_VFO,SDR1K_ANTS),
|
|
|
|
RIG_FRNG_END, },
|
|
|
|
|
|
|
|
.tuning_steps = { {SDR1K_MODES,1},
|
|
|
|
RIG_TS_END,
|
|
|
|
},
|
|
|
|
.priv = NULL, /* priv */
|
|
|
|
|
|
|
|
.rig_init = sdr1k_init,
|
|
|
|
.rig_open = sdr1k_open,
|
|
|
|
.rig_close = sdr1k_close,
|
|
|
|
.rig_cleanup = sdr1k_cleanup,
|
|
|
|
|
|
|
|
.set_freq = sdr1k_set_freq,
|
|
|
|
.get_freq = sdr1k_get_freq,
|
|
|
|
.set_ptt = sdr1k_set_ptt,
|
|
|
|
.reset = sdr1k_reset,
|
2003-11-16 17:22:06 +00:00
|
|
|
.set_level= sdr1k_set_level,
|
2003-09-28 15:36:57 +00:00
|
|
|
// .set_func = sdr1k_set_func,
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/* ************************************************************************* */
|
|
|
|
|
|
|
|
DECLARE_INITRIG_BACKEND(flexradio)
|
|
|
|
{
|
|
|
|
rig_debug(RIG_DEBUG_VERBOSE, "%s called\n", __FUNCTION__);
|
|
|
|
|
|
|
|
rig_register(&sdr1k_rig_caps);
|
|
|
|
|
|
|
|
return RIG_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ************************************************************************* */
|
|
|
|
|
|
|
|
int sdr1k_init(RIG *rig)
|
|
|
|
{
|
|
|
|
struct sdr1k_priv_data *priv;
|
|
|
|
|
|
|
|
priv = (struct sdr1k_priv_data*)malloc(sizeof(struct sdr1k_priv_data));
|
|
|
|
if (!priv) {
|
|
|
|
/* whoops! memory shortage! */
|
|
|
|
return -RIG_ENOMEM;
|
|
|
|
}
|
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
priv->dds_freq = RIG_FREQ_NONE;
|
2003-09-28 15:36:57 +00:00
|
|
|
priv->xtal = DEFAULT_XTAL;
|
2003-10-07 22:21:57 +00:00
|
|
|
priv->pll_mult = DEFAULT_PLL_MULT;
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
rig->state.priv = (void*)priv;
|
|
|
|
|
|
|
|
return RIG_OK;
|
|
|
|
}
|
|
|
|
|
2003-09-28 15:36:57 +00:00
|
|
|
static void pdelay(RIG *rig)
|
|
|
|
{
|
2003-10-07 22:21:57 +00:00
|
|
|
unsigned char r;
|
|
|
|
par_read_data(&rig->state.rigport, &r); /* ~1us */
|
2003-09-28 15:36:57 +00:00
|
|
|
}
|
|
|
|
|
2003-06-22 19:36:37 +00:00
|
|
|
int sdr1k_open(RIG *rig)
|
|
|
|
{
|
|
|
|
struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
|
|
|
|
|
|
|
|
priv->shadow[0] = 0;
|
|
|
|
priv->shadow[1] = 0;
|
|
|
|
priv->shadow[2] = 0;
|
|
|
|
priv->shadow[3] = 0;
|
|
|
|
|
|
|
|
sdr1k_reset(rig, 1);
|
|
|
|
|
|
|
|
return RIG_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
int sdr1k_close(RIG *rig)
|
|
|
|
{
|
2003-10-07 22:21:57 +00:00
|
|
|
/* TODO: release relays? */
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
return RIG_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
int sdr1k_cleanup(RIG *rig)
|
|
|
|
{
|
|
|
|
struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
|
|
|
|
|
|
|
|
if (priv) {
|
|
|
|
free(priv);
|
|
|
|
}
|
|
|
|
rig->state.priv = NULL;
|
|
|
|
|
|
|
|
return RIG_OK;
|
|
|
|
}
|
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
static int set_band(RIG *rig, freq_t freq)
|
2003-06-22 19:36:37 +00:00
|
|
|
{
|
2003-10-07 22:21:57 +00:00
|
|
|
int band, ret;
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
/* set_band */
|
|
|
|
if (freq <= MHz(2.25))
|
|
|
|
band = 0;
|
|
|
|
else if ( freq <= MHz(5.5))
|
|
|
|
band = 1;
|
|
|
|
else if (freq <= MHz(11))
|
|
|
|
band = 3; /* due to wiring mistake on board */
|
|
|
|
else if (freq <= MHz(22))
|
|
|
|
band = 2; /* due to wiring mistake on board */
|
|
|
|
else if (freq <= MHz(37.5))
|
|
|
|
band = 4;
|
|
|
|
else
|
|
|
|
band = 5;
|
2003-09-28 15:36:57 +00:00
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
ret = write_latch (rig, L_BAND, 1 << band, 0x3f);
|
|
|
|
|
2004-02-08 17:41:52 +00:00
|
|
|
rig_debug(RIG_DEBUG_VERBOSE, "%s %lld band %d\n", __FUNCTION__, (long long)freq, band);
|
2003-09-28 15:36:57 +00:00
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
return ret;
|
|
|
|
}
|
2003-06-22 19:36:37 +00:00
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
/*
|
|
|
|
* set DDS frequency.
|
|
|
|
* NB: due to spur reduction, effective frequency might not be the expected one
|
|
|
|
*/
|
|
|
|
int sdr1k_set_freq(RIG *rig, vfo_t vfo, freq_t freq)
|
|
|
|
{
|
|
|
|
struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
|
|
|
|
int i;
|
|
|
|
double ftw;
|
|
|
|
double DDS_step_size;
|
|
|
|
freq_t frqval;
|
|
|
|
int spur_red = 1;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = set_band(rig, freq);
|
|
|
|
if (ret != RIG_OK)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* Calculate DDS step for spu reduction
|
|
|
|
* DDS steps = 3051.7578125Hz
|
|
|
|
*/
|
|
|
|
DDS_step_size = ((double)priv->xtal * priv->pll_mult ) / 65536;
|
|
|
|
rig_debug(RIG_DEBUG_VERBOSE, "%s DDS step size %g %g %g\n", __FUNCTION__, DDS_step_size, (double)freq / DDS_step_size,
|
|
|
|
rint((double)freq / DDS_step_size));
|
|
|
|
if (spur_red)
|
|
|
|
frqval = (freq_t) (DDS_step_size * rint((double)freq / DDS_step_size));
|
|
|
|
else
|
|
|
|
frqval = freq;
|
2003-06-22 19:36:37 +00:00
|
|
|
|
2004-02-08 17:41:52 +00:00
|
|
|
rig_debug(RIG_DEBUG_VERBOSE, "%s curr %lld frqval %lld\n", __FUNCTION__, (long long)freq, (long long)frqval);
|
2003-10-07 22:21:57 +00:00
|
|
|
|
|
|
|
if (priv->dds_freq == frqval) {
|
|
|
|
return RIG_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*** */
|
|
|
|
ftw = (double)frqval / priv->xtal ;
|
2003-06-22 19:36:37 +00:00
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
for (i = 0; i<6; i++) {
|
|
|
|
unsigned word;
|
|
|
|
|
|
|
|
if (spur_red && i==2)
|
|
|
|
word = 128;
|
|
|
|
else if (spur_red && i>2)
|
|
|
|
word = 0;
|
|
|
|
else {
|
|
|
|
word = (unsigned)(ftw * 256);
|
|
|
|
ftw = ftw*256 - word;
|
|
|
|
}
|
2003-09-28 15:36:57 +00:00
|
|
|
rig_debug(RIG_DEBUG_TRACE, "DDS %d [%02x]\n", i, word);
|
2003-10-07 22:21:57 +00:00
|
|
|
|
|
|
|
ret = dds_write_reg (rig, 4+i, word);
|
|
|
|
if (ret != RIG_OK)
|
|
|
|
return ret;
|
2003-06-22 19:36:37 +00:00
|
|
|
}
|
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
priv->dds_freq = frqval;
|
|
|
|
|
|
|
|
return ret;
|
2003-06-22 19:36:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int sdr1k_get_freq(RIG *rig, vfo_t vfo, freq_t *freq)
|
|
|
|
{
|
2003-10-07 22:21:57 +00:00
|
|
|
struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
|
|
|
|
|
|
|
|
*freq = priv->dds_freq;
|
2004-02-08 17:41:52 +00:00
|
|
|
rig_debug(RIG_DEBUG_TRACE,"%s: %lld\n", __FUNCTION__, (long long)priv->dds_freq);
|
2003-10-07 22:21:57 +00:00
|
|
|
|
2003-06-22 19:36:37 +00:00
|
|
|
return RIG_OK;
|
|
|
|
}
|
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
/* Set DAC multiplier value */
|
|
|
|
static int DAC_mult(RIG *rig, unsigned mult)
|
|
|
|
{
|
|
|
|
rig_debug(RIG_DEBUG_TRACE, "DAC [%02x,%02x]\n", mult>>8, mult&0xff);
|
|
|
|
|
|
|
|
/* Output Shape Key I Mult */
|
|
|
|
dds_write_reg (rig, 0x21, mult >> 8);
|
|
|
|
dds_write_reg (rig, 0x22, mult & 0xff);
|
2003-06-22 19:36:37 +00:00
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
/* Output Shape Key Q Mult */
|
|
|
|
dds_write_reg (rig, 0x23, mult >> 8);
|
|
|
|
dds_write_reg (rig, 0x24, mult & 0xff);
|
|
|
|
|
|
|
|
return RIG_OK;
|
|
|
|
}
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
int sdr1k_reset (RIG *rig, reset_t reset)
|
|
|
|
{
|
2003-10-07 22:21:57 +00:00
|
|
|
/* Reset all Latches (relays off) */
|
2003-06-22 19:36:37 +00:00
|
|
|
write_latch (rig, L_BAND, 0x00, 0xff);
|
|
|
|
write_latch (rig, L_DDS1, 0x00, 0xff);
|
2003-10-07 22:21:57 +00:00
|
|
|
write_latch (rig, L_DDS0, 0x00, 0xff);
|
|
|
|
write_latch (rig, L_EXT, 0x00, 0xff);
|
|
|
|
|
|
|
|
/* Reset DDS */
|
|
|
|
write_latch (rig, L_DDS1, RESET|WRB, 0xff); /* reset the DDS chip */
|
|
|
|
write_latch (rig, L_DDS1, WRB, 0xff); /* leave WRB high */
|
|
|
|
|
|
|
|
dds_write_reg (rig, 0x1d, COMP_PD); /* Power down comparator */
|
|
|
|
/* TODO: add PLL multiplier property and logic */
|
|
|
|
dds_write_reg (rig, 0x1e, BYPASS_PLL); /* Bypass PLL */
|
|
|
|
|
|
|
|
dds_write_reg (rig, 0x20, BYPASS_SINC|OSK_EN);/* Bypass Inverse Sinc and enable DAC */
|
|
|
|
DAC_mult(rig, DEFAULT_DAC_MULT); /* Set DAC multiplier value */
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
return RIG_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
int sdr1k_set_ptt (RIG *rig, vfo_t vfo, ptt_t ptt)
|
|
|
|
{
|
2003-10-07 22:21:57 +00:00
|
|
|
return set_bit(rig, L_BAND, 6, ptt == RIG_PTT_ON);
|
2003-06-22 19:36:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2003-11-16 17:22:06 +00:00
|
|
|
int sdr1k_set_level (RIG *rig, vfo_t vfo, setting_t level, value_t val)
|
|
|
|
{
|
2004-05-17 21:09:45 +00:00
|
|
|
rig_debug(RIG_DEBUG_TRACE,"%s: %s %d\n", __FUNCTION__, rig_strlevel(level), val.i);
|
2003-11-16 17:22:06 +00:00
|
|
|
|
|
|
|
switch (level) {
|
|
|
|
case RIG_LEVEL_PREAMP:
|
|
|
|
return set_bit(rig, L_EXT, 7, !(val.i == rig->caps->preamp[0]));
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -RIG_EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
int
|
|
|
|
write_latch (RIG *rig, latch_t which, unsigned value, unsigned mask)
|
2003-06-22 19:36:37 +00:00
|
|
|
{
|
|
|
|
struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
|
|
|
|
port_t *pport = &rig->state.rigport;
|
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
if (!(L_EXT <= which && which <= L_DDS1))
|
|
|
|
return -RIG_EINVAL;
|
2003-06-22 19:36:37 +00:00
|
|
|
|
2003-09-28 15:36:57 +00:00
|
|
|
par_lock (pport);
|
2003-06-22 19:36:37 +00:00
|
|
|
priv->shadow[which] = (priv->shadow[which] & ~mask) | (value & mask);
|
|
|
|
par_write_data (pport, priv->shadow[which]);
|
2003-09-28 15:36:57 +00:00
|
|
|
pdelay(rig);
|
2003-06-22 19:36:37 +00:00
|
|
|
par_write_control (pport, 0x0F ^ (1 << which));
|
2003-09-28 15:36:57 +00:00
|
|
|
pdelay(rig);
|
2003-06-22 19:36:37 +00:00
|
|
|
par_write_control (pport, 0x0F);
|
2003-09-28 15:36:57 +00:00
|
|
|
pdelay(rig);
|
|
|
|
par_unlock (pport);
|
2003-10-07 22:21:57 +00:00
|
|
|
|
|
|
|
return RIG_OK;
|
2003-06-22 19:36:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
int
|
|
|
|
dds_write_reg (RIG *rig, unsigned addr, unsigned data)
|
2003-06-22 19:36:37 +00:00
|
|
|
{
|
2003-10-07 22:21:57 +00:00
|
|
|
#if 0
|
2003-06-22 19:36:37 +00:00
|
|
|
write_latch (rig, L_DDS1, addr & 0x3f, 0x3f);
|
|
|
|
write_latch (rig, L_DDS0, data, 0xff);
|
|
|
|
write_latch (rig, L_DDS1, 0x40, 0x40);
|
|
|
|
write_latch (rig, L_DDS1, 0x00, 0x40);
|
2003-10-07 22:21:57 +00:00
|
|
|
#else
|
|
|
|
/* set up data bits */
|
|
|
|
write_latch (rig, L_DDS0, data, 0xff);
|
|
|
|
|
|
|
|
/* set up address bits with WRB high */
|
|
|
|
//write_latch (rig, L_DDS1, addr & 0x3f, 0x3f);
|
|
|
|
write_latch (rig, L_DDS1, WRB | addr, 0xff);
|
|
|
|
|
|
|
|
/* send write command with WRB low */
|
|
|
|
write_latch (rig, L_DDS1, addr, 0xff);
|
|
|
|
|
|
|
|
/* return WRB high */
|
|
|
|
write_latch (rig, L_DDS1, WRB, 0xff);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return RIG_OK;
|
2003-06-22 19:36:37 +00:00
|
|
|
}
|
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
int
|
|
|
|
set_bit (RIG *rig, latch_t reg, unsigned bit, unsigned state)
|
2003-06-22 19:36:37 +00:00
|
|
|
{
|
2003-10-07 22:21:57 +00:00
|
|
|
unsigned val;
|
2003-06-22 19:36:37 +00:00
|
|
|
|
|
|
|
val = state ? 1<<bit : 0;
|
|
|
|
|
2003-10-07 22:21:57 +00:00
|
|
|
return write_latch (rig, reg, val, 1<<bit);
|
2003-06-22 19:36:37 +00:00
|
|
|
}
|
|
|
|
|