kopia lustrzana https://github.com/Hamlib/Hamlib
work based on Gerald's CRig.cls
git-svn-id: https://hamlib.svn.sourceforge.net/svnroot/hamlib/trunk@1560 7ae35d74-ebe9-4afe-98af-79ac388436b8Hamlib-1.2.0
Stéphane Fillod, F8CFE
rodzic
2acf79bcee
commit
9052ad41c0
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@ -2,7 +2,7 @@
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* Hamlib Rotator backend - SDR-1000
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* Copyright (c) 2003 by Stephane Fillod
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*
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* $Id: sdr1k.c,v 1.2 2003-09-28 15:36:57 fillods Exp $
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* $Id: sdr1k.c,v 1.3 2003-10-07 22:21:57 fillods Exp $
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*
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* This library is free software; you can redistribute it and/or modify
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* it under the terms of the GNU Library General Public License as
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@ -27,9 +27,7 @@
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#include <stdlib.h>
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#include <string.h> /* String function definitions */
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#include <unistd.h> /* UNIX standard function definitions */
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#ifdef HAVE_SYS_IOCTL_H
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#include <sys/ioctl.h>
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#endif
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#include <math.h>
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#include "hamlib/rig.h"
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#include "serial.h"
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@ -50,16 +48,36 @@ static int sdr1k_set_ptt (RIG *rig, vfo_t vfo, ptt_t ptt);
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typedef enum { L_EXT = 0, L_BAND = 1, L_DDS0 = 2, L_DDS1 = 3 } latch_t;
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static void write_latch (RIG *rig, latch_t which, int value, int mask);
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static void write_reg (RIG *rig, int addr, int data);
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static void set_bit (RIG *rig, latch_t reg, int bit, int state);
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#define TR 0x40
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#define MUTE 0x80
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#define GAIN 0x80
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#define WRB 0x40
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#define RESET 0x80
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/* DDS Control Constants */
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#define COMP_PD 0x10 /* DDS Comparator power down */
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#define DIG_PD 0x01 /* DDS Digital Power down */
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#define BYPASS_PLL 0x20 /* Bypass DDS PLL */
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#define INT_IOUD 0x01 /* Internal IO Update */
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#define OSK_EN 0x20 /* Offset Shift Keying enable */
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#define OSK_INT 0x10 /* Offset Shift Keying */
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#define BYPASS_SINC 0x40 /* Bypass Inverse Sinc Filter */
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#define PLL_RANGE 0x40 /* Set PLL Range */
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static int write_latch (RIG *rig, latch_t which, unsigned value, unsigned mask);
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static int dds_write_reg (RIG *rig, unsigned addr, unsigned data);
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static int set_bit (RIG *rig, latch_t reg, unsigned bit, unsigned state);
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#define DEFAULT_XTAL MHz(200)
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#define DEFAULT_PLL_MULT 1
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#define DEFAULT_DAC_MULT 4095
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struct sdr1k_priv_data {
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int shadow[4]; /* shadow latches */
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unsigned shadow[4]; /* shadow latches */
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freq_t dds_freq; /* current freq */
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freq_t xtal; /* base XTAL */
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int pll_mult; /* PLL mult */
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};
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@ -95,14 +113,18 @@ struct sdr1k_priv_data {
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* assert (pin < 8 and pin > 0), "Out of range 1..7"
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* self.set_bit(0, pin-1, on)
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*
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* set_conf(XTAL)
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* def read_input_pin
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*
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* set_conf(XTAL,PLL_mult,spur_red)
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*
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* What about IOUD_Clock?
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*/
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const struct rig_caps sdr1k_rig_caps = {
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.rig_model = RIG_MODEL_SDR1000,
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.model_name = "SDR-1000",
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.mfg_name = "Flex-radio",
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.version = "0.1.1",
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.version = "0.1.2",
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.copyright = "LGPL",
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.status = RIG_STATUS_NEW,
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.rig_type = RIG_TYPE_TUNER,
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@ -124,7 +146,7 @@ const struct rig_caps sdr1k_rig_caps = {
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.vfo_ops = RIG_OP_NONE,
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.transceive = RIG_TRN_OFF,
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.attenuator = { RIG_DBLST_END, },
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.preamp = { 20, RIG_DBLST_END, },
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.preamp = { 14, RIG_DBLST_END, },
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.rx_range_list1 = { {.start=Hz(1),.end=MHz(65),.modes=SDR1K_MODES,
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.low_power=-1,.high_power=-1,SDR1K_VFO},
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@ -187,8 +209,9 @@ int sdr1k_init(RIG *rig)
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return -RIG_ENOMEM;
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}
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rig->state.current_freq = RIG_FREQ_NONE;
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priv->dds_freq = RIG_FREQ_NONE;
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priv->xtal = DEFAULT_XTAL;
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priv->pll_mult = DEFAULT_PLL_MULT;
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rig->state.priv = (void*)priv;
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@ -197,7 +220,8 @@ int sdr1k_init(RIG *rig)
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static void pdelay(RIG *rig)
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{
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usleep(1);
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unsigned char r;
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par_read_data(&rig->state.rigport, &r); /* ~1us */
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}
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int sdr1k_open(RIG *rig)
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@ -211,15 +235,12 @@ int sdr1k_open(RIG *rig)
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sdr1k_reset(rig, 1);
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write_latch (rig, L_DDS1, 0x00, 0xC0); /* Reset low, WRS/ low */
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write_reg (rig, 0x20, 0x40);
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return RIG_OK;
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}
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int sdr1k_close(RIG *rig)
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{
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/* place holder.. */
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/* TODO: release relays? */
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return RIG_OK;
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}
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@ -236,11 +257,9 @@ int sdr1k_cleanup(RIG *rig)
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return RIG_OK;
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}
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int sdr1k_set_freq(RIG *rig, vfo_t vfo, freq_t freq)
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static int set_band(RIG *rig, freq_t freq)
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{
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struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
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int i, band;
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double ftw;
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int band, ret;
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/* set_band */
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if (freq <= MHz(2.25))
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@ -256,65 +275,136 @@ int sdr1k_set_freq(RIG *rig, vfo_t vfo, freq_t freq)
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else
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band = 5;
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ret = write_latch (rig, L_BAND, 1 << band, 0x3f);
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rig_debug(RIG_DEBUG_VERBOSE, "%s %lld band %d\n", __FUNCTION__, freq, band);
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write_latch (rig, L_BAND, 1 << band, 0x3f);
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return ret;
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}
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ftw = (double)freq / priv->xtal ;
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/*
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* set DDS frequency.
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* NB: due to spur reduction, effective frequency might not be the expected one
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*/
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int sdr1k_set_freq(RIG *rig, vfo_t vfo, freq_t freq)
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{
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struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
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int i;
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double ftw;
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double DDS_step_size;
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freq_t frqval;
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int spur_red = 1;
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int ret;
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for (i = 0; i<6; i++) {
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int word;
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ret = set_band(rig, freq);
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if (ret != RIG_OK)
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return ret;
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word = (int)(ftw * 256);
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ftw = ftw*256 - word;
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rig_debug(RIG_DEBUG_TRACE, "DDS %d [%02x]\n", i, word);
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write_reg (rig, 4+i, word);
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/* Calculate DDS step for spu reduction
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* DDS steps = 3051.7578125Hz
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*/
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DDS_step_size = ((double)priv->xtal * priv->pll_mult ) / 65536;
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rig_debug(RIG_DEBUG_VERBOSE, "%s DDS step size %g %g %g\n", __FUNCTION__, DDS_step_size, (double)freq / DDS_step_size,
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rint((double)freq / DDS_step_size));
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if (spur_red)
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frqval = (freq_t) (DDS_step_size * rint((double)freq / DDS_step_size));
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else
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frqval = freq;
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rig_debug(RIG_DEBUG_VERBOSE, "%s curr %lld frqval %lld\n", __FUNCTION__, freq, frqval);
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if (priv->dds_freq == frqval) {
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return RIG_OK;
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}
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return RIG_OK;
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/*** */
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ftw = (double)frqval / priv->xtal ;
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for (i = 0; i<6; i++) {
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unsigned word;
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if (spur_red && i==2)
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word = 128;
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else if (spur_red && i>2)
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word = 0;
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else {
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word = (unsigned)(ftw * 256);
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ftw = ftw*256 - word;
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}
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rig_debug(RIG_DEBUG_TRACE, "DDS %d [%02x]\n", i, word);
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ret = dds_write_reg (rig, 4+i, word);
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if (ret != RIG_OK)
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return ret;
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}
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priv->dds_freq = frqval;
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return ret;
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}
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int sdr1k_get_freq(RIG *rig, vfo_t vfo, freq_t *freq)
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{
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*freq = rig->state.current_freq;
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struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
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*freq = priv->dds_freq;
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rig_debug(RIG_DEBUG_TRACE,"%s: %lld\n", __FUNCTION__, priv->dds_freq);
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return RIG_OK;
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}
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/* Set DAC multiplier value */
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static int DAC_mult(RIG *rig, unsigned mult)
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{
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rig_debug(RIG_DEBUG_TRACE, "DAC [%02x,%02x]\n", mult>>8, mult&0xff);
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/* Output Shape Key I Mult */
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dds_write_reg (rig, 0x21, mult >> 8);
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dds_write_reg (rig, 0x22, mult & 0xff);
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/* Output Shape Key Q Mult */
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dds_write_reg (rig, 0x23, mult >> 8);
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dds_write_reg (rig, 0x24, mult & 0xff);
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return RIG_OK;
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}
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int sdr1k_reset (RIG *rig, reset_t reset)
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{
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port_t *pport = &rig->state.rigport;
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par_lock (pport);
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par_write_control (pport, 0x0F);
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pdelay(rig);
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par_unlock (pport);
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write_latch (rig, L_EXT, 0x00, 0xff);
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/* Reset all Latches (relays off) */
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write_latch (rig, L_BAND, 0x00, 0xff);
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write_latch (rig, L_DDS0, 0x80, 0xff); /* hold DDS in reset */
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write_latch (rig, L_DDS1, 0x00, 0xff);
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write_latch (rig, L_DDS0, 0x00, 0xff);
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write_latch (rig, L_EXT, 0x00, 0xff);
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/* Reset DDS */
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write_latch (rig, L_DDS1, RESET|WRB, 0xff); /* reset the DDS chip */
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write_latch (rig, L_DDS1, WRB, 0xff); /* leave WRB high */
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dds_write_reg (rig, 0x1d, COMP_PD); /* Power down comparator */
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/* TODO: add PLL multiplier property and logic */
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dds_write_reg (rig, 0x1e, BYPASS_PLL); /* Bypass PLL */
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dds_write_reg (rig, 0x20, BYPASS_SINC|OSK_EN);/* Bypass Inverse Sinc and enable DAC */
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DAC_mult(rig, DEFAULT_DAC_MULT); /* Set DAC multiplier value */
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return RIG_OK;
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}
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int sdr1k_set_ptt (RIG *rig, vfo_t vfo, ptt_t ptt)
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{
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set_bit(rig, 1, 6, ptt == RIG_PTT_ON);
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return RIG_OK;
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return set_bit(rig, L_BAND, 6, ptt == RIG_PTT_ON);
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}
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void
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write_latch (RIG *rig, latch_t which, int value, int mask)
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int
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write_latch (RIG *rig, latch_t which, unsigned value, unsigned mask)
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{
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struct sdr1k_priv_data *priv = (struct sdr1k_priv_data *)rig->state.priv;
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port_t *pport = &rig->state.rigport;
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if (!(0 <= which && which <= 3))
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return;
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if (!(L_EXT <= which && which <= L_DDS1))
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return -RIG_EINVAL;
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par_lock (pport);
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priv->shadow[which] = (priv->shadow[which] & ~mask) | (value & mask);
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@ -325,25 +415,44 @@ write_latch (RIG *rig, latch_t which, int value, int mask)
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par_write_control (pport, 0x0F);
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pdelay(rig);
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par_unlock (pport);
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return RIG_OK;
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}
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void
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write_reg (RIG *rig, int addr, int data)
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int
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dds_write_reg (RIG *rig, unsigned addr, unsigned data)
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{
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#if 0
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write_latch (rig, L_DDS1, addr & 0x3f, 0x3f);
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write_latch (rig, L_DDS0, data, 0xff);
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write_latch (rig, L_DDS1, 0x40, 0x40);
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write_latch (rig, L_DDS1, 0x00, 0x40);
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#else
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/* set up data bits */
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write_latch (rig, L_DDS0, data, 0xff);
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/* set up address bits with WRB high */
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//write_latch (rig, L_DDS1, addr & 0x3f, 0x3f);
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write_latch (rig, L_DDS1, WRB | addr, 0xff);
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/* send write command with WRB low */
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write_latch (rig, L_DDS1, addr, 0xff);
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/* return WRB high */
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write_latch (rig, L_DDS1, WRB, 0xff);
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#endif
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return RIG_OK;
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}
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void
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set_bit (RIG *rig, latch_t reg, int bit, int state)
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int
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set_bit (RIG *rig, latch_t reg, unsigned bit, unsigned state)
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{
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int val;
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unsigned val;
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val = state ? 1<<bit : 0;
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write_latch (rig, reg, val, 1<<bit);
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return write_latch (rig, reg, val, 1<<bit);
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}
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