kopia lustrzana https://github.com/espressif/esp-idf
6.4 KiB
6.4 KiB
| 1 | # field_name, | efuse_block, | bit_start, | bit_count, |comment # |
|---|---|
| 2 | # | (EFUSE_BLK0 | (0..255) | (1-256) | # |
| 3 | # | EFUSE_BLK1 | | | # |
| 4 | # | EFUSE_BLK3) | | | # |
| 5 | ########################################################################## |
| 6 | # !!!!!!!!!!! # |
| 7 | # this will generate new source files, next rebuild all the sources. |
| 8 | # !!!!!!!!!!! # |
| 9 | # EFUSE_RD_REPEAT_DATA BLOCK # |
| 10 | ############################## |
| 11 | # EFUSE_RD_WR_DIS_REG # |
| 12 | WR_DIS, EFUSE_BLK0, 0, 8, Write protection |
| 13 | WR_DIS.KEY0_RD_DIS, EFUSE_BLK0, 0, 1, Write protection for KEY0_RD_DIS |
| 14 | WR_DIS.GROUP_1, EFUSE_BLK0, 1, 1, Write protection for WDT_DELAY DIS_PAD_JTAG DIS_DOWNLOAD_ICACHE |
| 15 | WR_DIS.GROUP_2, EFUSE_BLK0, 2, 1, Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT SPI_BOOT_CRYPT_CNT XTS_KEY_LENGTH_256 SECURE_BOOT_EN |
| 16 | WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 2, 1, Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT [SPI_BOOT_CRYPT_CNT] XTS_KEY_LENGTH_256 SECURE_BOOT_EN |
| 17 | WR_DIS.GROUP_3, EFUSE_BLK0, 3, 1, Write protection for UART_PRINT_CONTROL FORCE_SEND_RESUME DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT ENABLE_SECURITY_DOWNLOAD FLASH_TPUW |
| 18 | WR_DIS.BLK0_RESERVED, EFUSE_BLK0, 4, 1, Write protection for BLK0_RESERVED |
| 19 | WR_DIS.SYS_DATA_PART0, EFUSE_BLK0, 5, 1, Write protection for EFUSE_BLK1. SYS_DATA_PART0 |
| 20 | WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 6, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART2 |
| 21 | WR_DIS.KEY0, EFUSE_BLK0, 7, 1, Write protection for EFUSE_BLK3. whole KEY0 |
| 22 | # EFUSE_RD_REPEAT_DATA0_REG # |
| 23 | RD_DIS, EFUSE_BLK0, 32, 2, Read protection |
| 24 | RD_DIS.KEY0, EFUSE_BLK0, 32, 2, Read protection for EFUSE_BLK3. KEY0 |
| 25 | RD_DIS.KEY0.LOW, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK3. KEY0 lower 128-bit key |
| 26 | RD_DIS.KEY0.HI, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK3. KEY0 higher 128-bit key |
| 27 | WDT_DELAY_SEL, EFUSE_BLK0, 34, 2, RTC WDT timeout threshold |
| 28 | DIS_PAD_JTAG, EFUSE_BLK0, 36, 1, Hardware Disable JTAG permanently |
| 29 | DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 37, 1, Disable ICache in Download mode |
| 30 | DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 38, 1, Disable flash encryption in Download boot mode |
| 31 | SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 39, 3, Enable SPI boot encrypt/decrypt. Odd number: enable; even number: disable |
| 32 | XTS_KEY_LENGTH_256, EFUSE_BLK0, 42, 1, Select XTS_AES key length. 1: 256-bit of whole block3; 0: Lower 128-bit of block3 |
| 33 | UART_PRINT_CONTROL, EFUSE_BLK0, 43, 2, Set UART boot message output mode. 00: Force print; 01: Low-level print controlled by GPIO 8; 10: High-level print controlled by GPIO 8; 11: Print force disabled |
| 34 | FORCE_SEND_RESUME, EFUSE_BLK0, 45, 1, Force ROM code to send an SPI flash resume command during SPI boot |
| 35 | DIS_DOWNLOAD_MODE, EFUSE_BLK0, 46, 1, Disable all download boot modes |
| 36 | DIS_DIRECT_BOOT, EFUSE_BLK0, 47, 1, Disable direct_boot mode |
| 37 | ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 48, 1, Enable secure UART download mode |
| 38 | FLASH_TPUW, EFUSE_BLK0, 49, 4, Configure flash startup delay after SoC being powered up (the unit is ms/2). When the value is 15 delay will be 7.5 ms |
| 39 | SECURE_BOOT_EN, EFUSE_BLK0, 53, 1, Enable secure boot |
| 40 | SECURE_VERSION, EFUSE_BLK0, 54, 4, Secure version for anti-rollback |
| 41 | # USER_DATA BLOCK# - System configuration |
| 42 | ####################### |
| 43 | USER_DATA, EFUSE_BLK1, 0, 88, User data block |
| 44 | USER_DATA.MAC_CUSTOM, EFUSE_BLK1, 0, 48, Custom MAC addr |
| 45 | # SYS_DATA_PART1 BLOCK# - System configuration |
| 46 | ####################### |
| 47 | MAC_FACTORY, EFUSE_BLK2, 40, 8, Factory MAC addr [0] |
| 48 | , EFUSE_BLK2, 32, 8, Factory MAC addr [1] |
| 49 | , EFUSE_BLK2, 24, 8, Factory MAC addr [2] |
| 50 | , EFUSE_BLK2, 16, 8, Factory MAC addr [3] |
| 51 | , EFUSE_BLK2, 8, 8, Factory MAC addr [4] |
| 52 | , EFUSE_BLK2, 0, 8, Factory MAC addr [5] |
| 53 | WAFER_VERSION, EFUSE_BLK2, 48, 3, EFUSE_WAFER_VERSION |
| 54 | PKG_VERSION, EFUSE_BLK2, 51, 3, EFUSE_PKG_VERSION |
| 55 | BLOCK2_VERSION, EFUSE_BLK2, 54, 3, EFUSE_BLOCK2_VERSION |
| 56 | RF_REF_I_BIAS_CONFIG, EFUSE_BLK2, 57, 4, EFUSE_RF_REF_I_BIAS_CONFIG |
| 57 | LDO_VOL_BIAS_CONFIG_LOW, EFUSE_BLK2, 61, 3, EFUSE_LDO_VOL_BIAS_CONFIG_LOW |
| 58 | LDO_VOL_BIAS_CONFIG_HIGH, EFUSE_BLK2, 64, 27, EFUSE_LDO_VOL_BIAS_CONFIG_HIGH |
| 59 | PVT_LOW, EFUSE_BLK2, 91, 5, EFUSE_PVT_LOW |
| 60 | PVT_HIGH, EFUSE_BLK2, 96, 10, EFUSE_PVT_HIGH |
| 61 | ADC_CALIBRATION_0, EFUSE_BLK2, 106, 22, EFUSE_ADC_CALIBRATION_0 |
| 62 | ADC_CALIBRATION_1, EFUSE_BLK2, 128, 32, EFUSE_ADC_CALIBRATION_1 |
| 63 | ADC_CALIBRATION_2, EFUSE_BLK2, 160, 32, EFUSE_ADC_CALIBRATION_2 |
| 64 | ################ |
| 65 | KEY0, EFUSE_BLK3, 0, 256, [256bit FE key] or [128bit FE key and 128key SB key] or [user data] |
| 66 | KEY0.FE_256BIT, EFUSE_BLK3, 0, 256, [256bit FE key] |
| 67 | KEY0.FE_128BIT, EFUSE_BLK3, 0, 128, [128bit FE key] |
| 68 | KEY0.SB_128BIT, EFUSE_BLK3, 128, 128, [128bit SB key] |