2021-11-06 09:23:21 +00:00
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# field_name, | efuse_block, | bit_start, | bit_count, |comment #
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2021-12-02 17:48:47 +00:00
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# | (EFUSE_BLK0 | (0..255) | (1-256) | #
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# | EFUSE_BLK1 | | | #
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# | EFUSE_BLK3) | | | #
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2021-11-06 09:23:21 +00:00
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##########################################################################
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# !!!!!!!!!!! #
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# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table"
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# this will generate new source files, next rebuild all the sources.
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# !!!!!!!!!!! #
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# EFUSE_RD_REPEAT_DATA BLOCK #
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##############################
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# EFUSE_RD_WR_DIS_REG #
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WR_DIS, EFUSE_BLK0, 0, 8, Write protection
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WR_DIS.KEY0_RD_DIS, EFUSE_BLK0, 0, 1, Write protection for KEY0_RD_DIS
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2021-12-02 17:48:47 +00:00
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WR_DIS.GROUP_1, EFUSE_BLK0, 1, 1, Write protection for WDT_DELAY DIS_PAD_JTAG DIS_DOWNLOAD_ICACHE
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WR_DIS.GROUP_2, EFUSE_BLK0, 2, 1, Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT SPI_BOOT_CRYPT_CNT XTS_KEY_LENGTH_256 SECURE_BOOT_EN
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WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 2, 1, Write protection for DOWNLOAD_DIS_MANUAL_ENCRYPT [SPI_BOOT_CRYPT_CNT] XTS_KEY_LENGTH_256 SECURE_BOOT_EN
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WR_DIS.GROUP_3, EFUSE_BLK0, 3, 1, Write protection for UART_PRINT_CONTROL FORCE_SEND_RESUME DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT ENABLE_SECURITY_DOWNLOAD FLASH_TPUW
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2021-11-06 09:23:21 +00:00
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WR_DIS.BLK0_RESERVED, EFUSE_BLK0, 4, 1, Write protection for BLK0_RESERVED
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WR_DIS.SYS_DATA_PART0, EFUSE_BLK0, 5, 1, Write protection for EFUSE_BLK1. SYS_DATA_PART0
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WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 6, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART2
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2021-12-02 17:48:47 +00:00
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WR_DIS.KEY0, EFUSE_BLK0, 7, 1, Write protection for EFUSE_BLK3. whole KEY0
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2021-11-06 09:23:21 +00:00
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# EFUSE_RD_REPEAT_DATA0_REG #
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2021-12-02 17:48:47 +00:00
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RD_DIS, EFUSE_BLK0, 32, 2, Read protection
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RD_DIS.KEY0, EFUSE_BLK0, 32, 2, Read protection for EFUSE_BLK3. KEY0
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RD_DIS.KEY0.LOW, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK3. KEY0 lower 128-bit key
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RD_DIS.KEY0.HI, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK3. KEY0 higher 128-bit key
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2021-11-06 09:23:21 +00:00
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2021-12-02 17:48:47 +00:00
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WDT_DELAY_SEL, EFUSE_BLK0, 34, 2, RTC WDT timeout threshold
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DIS_PAD_JTAG, EFUSE_BLK0, 36, 1, Hardware Disable JTAG permanently
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DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 37, 1, Disable ICache in Download mode
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DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 38, 1, Disable flash encryption in Download boot mode
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SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 39, 3, Enable SPI boot encrypt/decrypt. Odd number: enable; even number: disable
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XTS_KEY_LENGTH_256, EFUSE_BLK0, 42, 1, Select XTS_AES key length. 1: 256-bit of whole block3; 0: Lower 128-bit of block3
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UART_PRINT_CONTROL, EFUSE_BLK0, 43, 2, Set UART boot message output mode. 00: Force print; 01: Low-level print controlled by GPIO 8; 10: High-level print controlled by GPIO 8; 11: Print force disabled
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FORCE_SEND_RESUME, EFUSE_BLK0, 45, 1, Force ROM code to send an SPI flash resume command during SPI boot
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DIS_DOWNLOAD_MODE, EFUSE_BLK0, 46, 1, Disable all download boot modes
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DIS_DIRECT_BOOT, EFUSE_BLK0, 47, 1, Disable direct_boot mode
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ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 48, 1, Enable secure UART download mode
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FLASH_TPUW, EFUSE_BLK0, 49, 4, Configure flash startup delay after SoC being powered up (the unit is ms/2). When the value is 15 delay will be 7.5 ms
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SECURE_BOOT_EN, EFUSE_BLK0, 53, 1, Enable secure boot
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SECURE_VERSION, EFUSE_BLK0, 54, 4, Secure version for anti-rollback
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2021-11-06 09:23:21 +00:00
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2021-12-02 17:48:47 +00:00
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# USER_DATA BLOCK# - System configuration
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2021-11-06 09:23:21 +00:00
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#######################
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2021-12-02 17:48:47 +00:00
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USER_DATA, EFUSE_BLK1, 0, 88, User data block
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USER_DATA.MAC_CUSTOM, EFUSE_BLK1, 0, 48, Custom MAC addr
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2021-11-06 09:23:21 +00:00
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# SYS_DATA_PART1 BLOCK# - System configuration
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#######################
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MAC_FACTORY, EFUSE_BLK2, 40, 8, Factory MAC addr [0]
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, EFUSE_BLK2, 32, 8, Factory MAC addr [1]
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, EFUSE_BLK2, 24, 8, Factory MAC addr [2]
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, EFUSE_BLK2, 16, 8, Factory MAC addr [3]
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, EFUSE_BLK2, 8, 8, Factory MAC addr [4]
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, EFUSE_BLK2, 0, 8, Factory MAC addr [5]
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WAFER_VERSION, EFUSE_BLK2, 48, 3, EFUSE_WAFER_VERSION
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PKG_VERSION, EFUSE_BLK2, 51, 3, EFUSE_PKG_VERSION
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BLOCK2_VERSION, EFUSE_BLK2, 54, 3, EFUSE_BLOCK2_VERSION
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RF_REF_I_BIAS_CONFIG, EFUSE_BLK2, 57, 4, EFUSE_RF_REF_I_BIAS_CONFIG
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LDO_VOL_BIAS_CONFIG_LOW, EFUSE_BLK2, 61, 3, EFUSE_LDO_VOL_BIAS_CONFIG_LOW
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LDO_VOL_BIAS_CONFIG_HIGH, EFUSE_BLK2, 64, 27, EFUSE_LDO_VOL_BIAS_CONFIG_HIGH
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PVT_LOW, EFUSE_BLK2, 91, 5, EFUSE_PVT_LOW
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PVT_HIGH, EFUSE_BLK2, 96, 10, EFUSE_PVT_HIGH
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ADC_CALIBRATION_0, EFUSE_BLK2, 106, 22, EFUSE_ADC_CALIBRATION_0
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ADC_CALIBRATION_1, EFUSE_BLK2, 128, 32, EFUSE_ADC_CALIBRATION_1
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ADC_CALIBRATION_2, EFUSE_BLK2, 160, 32, EFUSE_ADC_CALIBRATION_2
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################
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KEY0, EFUSE_BLK3, 0, 256, [256bit FE key] or [128bit FE key and 128key SB key] or [user data]
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2021-12-02 17:48:47 +00:00
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KEY0.FE_256BIT, EFUSE_BLK3, 0, 256, [256bit FE key]
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KEY0.FE_128BIT, EFUSE_BLK3, 0, 128, [128bit FE key]
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KEY0.SB_128BIT, EFUSE_BLK3, 128, 128, [128bit SB key]
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