e6d23a35ec
gdma: dynamic alloc DMA channels
2021-01-13 10:52:27 +08:00
dc7bdb9857
adjust lightsleep overhead time and cali slowclk
2021-01-06 03:40:28 +00:00
eb788deb03
esp_hw_support: merge C3 changes to master
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Merge RTC related C3 changes to master
2020-12-30 12:20:41 +08:00
1b0442b963
Merge branch 'feature/unify_rtc_fast_mem_as_heap_config_across_chips' into 'master'
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esp_system: make rtc fast memory to heap configuration unified across chips
Closes IDF-2503
See merge request espressif/esp-idf!11693
2020-12-29 11:41:05 +08:00
c3ba995f2c
Merge branch 'ci/ccomp_performance_tests' into 'master'
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unit_test: Refactor all performance tests that rely on cache compensated timer
See merge request espressif/esp-idf!11709
2020-12-24 13:44:52 +08:00
880a63b2e9
esp_system: make rtc fast memory to heap configuration unified across chips
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Closes IDF-2503
2020-12-24 09:46:35 +05:30
705d797b41
Merge branch 'feature/esp32c3_drivers' into 'master'
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driver: Add esp32c3
Closes IDF-2363
See merge request espressif/esp-idf!11650
2020-12-23 08:43:31 +08:00
fa892eb017
soc: Explain units for rtc_clk_cal() function, fix typo
2020-12-23 09:53:24 +11:00
e338a2e3df
rtc: add function to en/disable the rtc clock
2020-12-23 09:53:24 +11:00
0a95151a75
unit_test: Refactor all performance tests that rely on cache compensated timer
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There is no ccomp timer on C3, which means our performance tests will start
failing again due to variance caused by cache misses.
This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail
performance test if CCOMP timer is supported on the target
2020-12-22 18:56:24 +11:00
06d6146445
fix rtc_gpio_desc_t compilation error
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Closes https://github.com/espressif/esp-idf/pull/6029
Closes https://github.com/espressif/esp-idf/issues/6301
Closes IDFGH-4470
Closes IDFGH-4167
2020-12-21 13:54:52 +05:30
0736c91d68
soc: Remove cache constants from soc.h
2020-12-17 15:34:13 +11:00
457ce080ae
AES: refactor and add HAL layer
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Refactor the AES driver and add HAL, LL and caps.
Add better support for running AES-GCM fully in hardware.
2020-12-10 09:04:47 +00:00
c29d93986d
soc: Add initial ESP32-C3 support
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From internal commit 7761d6e8
2020-11-30 11:12:56 +11:00
fb8b905539
uart: add uart support on esp32s3
2020-11-24 19:12:51 +08:00
c5fe158929
doc: fix wrong register description regarding to ethernet SMI
2020-11-16 13:30:49 +08:00
14944b181e
Merge branch 'fix/soc_caps_spi_dummy_output_esp32' into 'master'
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soc_caps.h: remove spi cap that is defined to 0
See merge request espressif/esp-idf!11203
2020-11-16 10:39:27 +08:00
099fca515d
Merge branch 'bugfix/move_crypto_caps' into 'master'
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SHA/RSA: moved all caps to soc_caps.h
Closes IDF-2300
See merge request espressif/esp-idf!11032
2020-11-13 11:06:44 +08:00
935e4b4d62
Merge branch 'feature/riscv_arch' into 'master'
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Add RISC-V support
Closes IDF-2359
See merge request espressif/esp-idf!11140
2020-11-13 07:50:31 +08:00
420aef1ffe
Updates for riscv support
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* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
longer signed/unsigned int).
Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00
caf83b88ba
Merge branch 'feature/bringup_i2c_for_s3' into 'master'
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I2C: Add support for esp32s3 and add source clock allocator
Closes IDF-2011
See merge request espressif/esp-idf!10923
2020-11-12 22:12:58 +08:00
6eee601cf6
i2c: Add supports on esp32s3
2020-11-12 11:32:45 +08:00
dc227c78e1
rmt: fix wrong signal assign on esp32
2020-11-12 10:31:38 +08:00
5b6c965e99
soc_caps.h: remove spi cap that is defined to 0
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According to the caps rule, for unsupported feature we don't define anything.
Remove the define 0 that violates this rule.
2020-11-12 10:29:42 +08:00
488f46acf5
SHA/RSA: moved all caps to soc_caps.h
2020-11-12 02:15:46 +00:00
66fb5a29bb
Whitespace: Automated whitespace fixes (large commit)
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Apply the pre-commit hook whitespace fixes to all files in the repo.
(Line endings, blank lines at end of file, trailing whitespace)
2020-11-11 07:36:35 +00:00
ff976867b3
rmt: split TX and RX in LL driver
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Split TX and RX function in LL driver.
Channel number is encoded in driver layer.
Added channel signal list in periph.c
2020-11-05 19:00:55 +08:00
9465af0066
rmt: support esp32s3
2020-11-05 19:00:55 +08:00
e4c8ec6174
timergroup: move interrupt index into peripheral description file
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1. Added timer_group_periph.c file, describing module global signals
(e.g. interrupt index)
2. Added more caps in soc_caps.h
2020-11-03 18:16:50 +08:00
35faecea1d
Merge branch 'feature/support_sigma_delta_on_s3' into 'master'
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sigma_delta: add periph signal list and support esp32-s3
See merge request espressif/esp-idf!10945
2020-10-30 17:22:02 +08:00
3bacf35310
esp_flash: support high capacity flash chips (32-bit address)
2020-10-29 18:20:11 +08:00
17808b3ff8
sigma_delta: add periph signal list and support esp32-s3
2020-10-29 11:06:28 +08:00
6b0a5af73e
soc: move implementations to esp_hw_support
2020-10-28 22:38:50 +08:00
79887fdc6c
soc: descriptive part occupy whole component
2020-10-28 07:21:29 +08:00
1f2e2fe8af
soc: separate abstraction, description and implementation
2020-02-11 14:30:42 +05:00
aaf119e930
flash(esp32s2): fix setting address field in spi user mode.
2020-02-07 16:10:51 +01:00
50466a5e4f
Merge branch 'bugfix/esp32s2_ldscripts' into 'master'
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esp32s2: LD script fixes/improvements and re-enable SystemView examples
Closes IDF-1357, IDF-1354, and IDF-1346
See merge request espressif/esp-idf!7431
2020-02-05 02:09:29 +08:00
354ce68dce
soc: move reserved regions out of memory_layout_utils.c
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These definitions have ended up being chip specific. Moving them into
respective soc_memory_layout.c makes the whole picture of memory
regions easier to see, and also makes adding support for new chips
easier.
2020-01-24 10:48:20 +01:00
70752baba4
esp32s2: add brownout detector support
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1. add brownout detector HAL for esp32 and esp32s2
2. enable brownout reset for esp32 rev. 1 and above
3. add approximate brownout detector levels for esp32s2
2020-01-23 13:44:19 +01:00
c7738f24fc
Merge branch 'bugfix/ledc_driver_enums' into 'master'
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driver: Avoid possible accidental mismatch between ledc_clk_src_t & ledc_clk_cfg_t enum
See merge request espressif/esp-idf!7021
2020-01-10 15:34:43 +08:00
a049e02d96
can: Refactor CAN to use HAL and LowLevel layers
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The following commit refactors the CAN driver such that
it is split into HAL and Lowlevel layers. The following
changes have also been made:
- Added bit field members to can_message_t as alternative
to message flags. Updated examples and docs accordingly
- Register field names and fields of can_dev_t updated
2020-01-09 16:13:51 +08:00
f676a3b190
driver, soc: update multichip support headers
2020-01-06 17:13:54 +08:00
52f8aa2adb
Merge branch 'feature/heap_non_os_build' into 'master'
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heap: make compatible with non-OS builds, remove target dependence
Closes IDF-1236
See merge request espressif/esp-idf!7051
2020-01-03 17:12:51 +08:00
d9534b3d6a
soc: fix backtraces containing ROM functions
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esp_ptr_executable would return false for pointers to ROM, which would
interrupt the backtrace. This makes ROM ranges recognized as
executable.
2020-01-02 18:42:46 +01:00
4bbfa6e494
Merge branch 'feature/soc_ledc_caps' into 'master'
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soc: add ledc_caps.h, replace target-based ifdefs with caps-based
See merge request espressif/esp-idf!6858
2019-12-30 18:47:11 +08:00
e4d45608d3
soc: add ledc_caps.h, replace target-based ifdefs with caps-based
2019-12-28 20:33:21 +00:00
3285ed116d
heap: make compatible with non-OS builds, remove target dependence
2019-12-27 12:40:06 +01:00
7baf7ce273
ethernet: optimise tx and rx
2019-12-24 11:18:31 +08:00
11fa11000f
spi: re-enable the unit tests for esp32s2beta
2019-12-23 10:22:59 +08:00
e8db1c4da0
Merge branch 'feature/enable_i2s_tests_on_esp32s2beta' into 'master'
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Enable i2s and freertos test/s on esp32s2beta
See merge request espressif/esp-idf!6790
2019-12-18 17:51:54 +08:00
morris