kopia lustrzana https://github.com/espressif/esp-idf
ethernet: optimise tx and rx
rodzic
fce6a9c735
commit
7baf7ce273
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@ -299,6 +299,8 @@ esp_err_t esp_eth_transmit(esp_eth_handle_t hdl, void *buf, uint32_t length)
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{
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esp_err_t ret = ESP_OK;
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esp_eth_driver_t *eth_driver = (esp_eth_driver_t *)hdl;
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ETH_CHECK(buf, "can't set buf to null", err, ESP_ERR_INVALID_ARG);
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ETH_CHECK(length, "buf length can't be zero", err, ESP_ERR_INVALID_ARG);
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ETH_CHECK(eth_driver, "ethernet driver handle can't be null", err, ESP_ERR_INVALID_ARG);
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esp_eth_mac_t *mac = eth_driver->mac;
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return mac->transmit(mac, buf, length);
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@ -310,6 +312,8 @@ esp_err_t esp_eth_receive(esp_eth_handle_t hdl, uint8_t *buf, uint32_t *length)
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{
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esp_err_t ret = ESP_OK;
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esp_eth_driver_t *eth_driver = (esp_eth_driver_t *)hdl;
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ETH_CHECK(buf && length, "can't set buf and length to null", err, ESP_ERR_INVALID_ARG);
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ETH_CHECK(*length > 60, "length can't be less than 60", err, ESP_ERR_INVALID_ARG);
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ETH_CHECK(eth_driver, "ethernet driver handle can't be null", err, ESP_ERR_INVALID_ARG);
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esp_eth_mac_t *mac = eth_driver->mac;
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return mac->receive(mac, buf, length);
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@ -397,8 +397,10 @@ static void emac_dm9051_task(void *arg)
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if (status & ISR_PR) {
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do {
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length = ETH_MAX_PACKET_SIZE;
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buffer = (uint8_t *)heap_caps_malloc(length, MALLOC_CAP_DMA);
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if (emac->parent.receive(&emac->parent, buffer, &length) == ESP_OK) {
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buffer = heap_caps_malloc(length, MALLOC_CAP_DMA);
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if (!buffer) {
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ESP_LOGE(TAG, "no mem for receive buffer");
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} else if (emac->parent.receive(&emac->parent, buffer, &length) == ESP_OK) {
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/* pass the buffer to stack (e.g. TCP/IP layer) */
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if (length) {
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emac->eth->stack_input(emac->eth, buffer, length);
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@ -597,8 +599,6 @@ static esp_err_t emac_dm9051_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint32_t
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{
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esp_err_t ret = ESP_OK;
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emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
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MAC_CHECK(buf, "can't set buf to null", err, ESP_ERR_INVALID_ARG);
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MAC_CHECK(length, "buf length can't be zero", err, ESP_ERR_INVALID_ARG);
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/* Check if last transmit complete */
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uint8_t tcr = 0;
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MAC_CHECK(dm9051_register_read(emac, DM9051_TCR, &tcr) == ESP_OK, "read TCR failed", err, ESP_FAIL);
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@ -620,7 +620,6 @@ static esp_err_t emac_dm9051_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32_t
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{
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esp_err_t ret = ESP_OK;
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emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
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MAC_CHECK(buf && length, "can't set buf and length to null", err, ESP_ERR_INVALID_ARG);
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uint8_t rxbyte = 0;
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uint16_t rx_len = 0;
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__attribute__((aligned(4))) dm9051_rx_header_t header; // SPI driver needs the rx buffer 4 byte align
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@ -214,12 +214,8 @@ static esp_err_t emac_esp32_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint32_t
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{
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esp_err_t ret = ESP_OK;
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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MAC_CHECK(buf, "can't set buf to null", err, ESP_ERR_INVALID_ARG);
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MAC_CHECK(length, "buf length can't be zero", err, ESP_ERR_INVALID_ARG);
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/* Check if the descriptor is owned by the Ethernet DMA (when 1) or CPU (when 0) */
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MAC_CHECK(emac_hal_get_tx_desc_owner(&emac->hal) == EMAC_DMADESC_OWNER_CPU,
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"CPU doesn't own the Tx Descriptor", err, ESP_ERR_INVALID_STATE);
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emac_hal_transmit_frame(&emac->hal, buf, length);
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uint32_t sent_len = emac_hal_transmit_frame(&emac->hal, buf, length);
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MAC_CHECK(sent_len == length, "insufficient TX buffer size", err, ESP_ERR_INVALID_SIZE);
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return ESP_OK;
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err:
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return ret;
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@ -228,20 +224,17 @@ err:
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static esp_err_t emac_esp32_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32_t *length)
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{
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esp_err_t ret = ESP_OK;
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uint32_t expected_len = *length;
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emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
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MAC_CHECK(buf && length, "can't set buf and length to null", err, ESP_ERR_INVALID_ARG);
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uint32_t receive_len = emac_hal_receive_frame(&emac->hal, buf, *length, &emac->frames_remain);
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uint32_t receive_len = emac_hal_receive_frame(&emac->hal, buf, expected_len, &emac->frames_remain);
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/* we need to check the return value in case the buffer size is not enough */
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if (*length < receive_len) {
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ESP_LOGE(TAG, "buffer size too small");
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/* tell upper layer the size we need */
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*length = receive_len;
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ret = ESP_ERR_INVALID_SIZE;
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goto err;
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}
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ESP_LOGD(TAG, "receive len= %d", receive_len);
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MAC_CHECK(expected_len >= receive_len, "received buffer longer than expected", err, ESP_ERR_INVALID_SIZE);
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*length = receive_len;
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return ESP_OK;
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err:
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*length = expected_len;
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return ret;
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}
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@ -255,8 +248,10 @@ static void emac_esp32_rx_task(void *arg)
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ulTaskNotifyTake(pdFALSE, portMAX_DELAY);
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do {
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length = ETH_MAX_PACKET_SIZE;
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buffer = (uint8_t *)malloc(length);
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if (emac_esp32_receive(&emac->parent, buffer, &length) == ESP_OK) {
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buffer = malloc(length);
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if (!buffer) {
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ESP_LOGE(TAG, "no mem for receive buffer");
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} else if (emac_esp32_receive(&emac->parent, buffer, &length) == ESP_OK) {
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/* pass the buffer to stack (e.g. TCP/IP layer) */
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if (length) {
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emac->eth->stack_input(emac->eth, buffer, length);
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@ -291,9 +286,9 @@ static esp_err_t emac_esp32_init(esp_eth_mac_t *mac)
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esp_eth_mediator_t *eth = emac->eth;
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/* enable peripheral clock */
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periph_module_enable(PERIPH_EMAC_MODULE);
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/* enable clock, config gpio, etc */
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/* init clock, config gpio, etc */
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emac_hal_lowlevel_init(&emac->hal);
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/* init gpio used by gpio */
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/* init gpio used by smi interface */
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emac_esp32_init_smi_gpio(emac);
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MAC_CHECK(eth->on_state_changed(eth, ETH_STATE_LLINIT, NULL) == ESP_OK, "lowlevel init failed", err, ESP_FAIL);
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/* software reset */
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@ -66,7 +66,7 @@ static esp_err_t emac_opencores_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32
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static IRAM_ATTR void emac_opencores_isr_handler(void *args)
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{
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emac_opencores_t *emac = (emac_opencores_t*) args;
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emac_opencores_t *emac = (emac_opencores_t *) args;
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BaseType_t high_task_wakeup;
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uint32_t status = REG_READ(OPENETH_INT_SOURCE_REG);
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@ -94,10 +94,12 @@ static void emac_opencores_rx_task(void *arg)
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uint32_t length = 0;
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while (1) {
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if (ulTaskNotifyTake(pdFALSE, portMAX_DELAY)) {
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while(true) {
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buffer = (uint8_t *)malloc(ETH_MAX_PACKET_SIZE);
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while (true) {
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length = ETH_MAX_PACKET_SIZE;
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if (emac_opencores_receive(&emac->parent, buffer, &length) == ESP_OK) {
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buffer = malloc(length);
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if (!buffer) {
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ESP_LOGE(TAG, "no mem for receive buffer");
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} else if (emac_opencores_receive(&emac->parent, buffer, &length) == ESP_OK) {
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// pass the buffer to the upper layer
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if (length) {
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emac->eth->stack_input(emac->eth, buffer, length);
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@ -232,8 +234,6 @@ static esp_err_t emac_opencores_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint3
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{
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esp_err_t ret = ESP_OK;
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emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent);
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MAC_CHECK(buf, "can't set buf to null", err, ESP_ERR_INVALID_ARG);
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MAC_CHECK(length, "buf length can't be zero", err, ESP_ERR_INVALID_ARG);
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MAC_CHECK(length < DMA_BUF_SIZE * TX_BUF_COUNT, "insufficient TX buffer size", err, ESP_ERR_INVALID_SIZE);
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uint32_t bytes_remaining = length;
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@ -243,7 +243,7 @@ static esp_err_t emac_opencores_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint3
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while (bytes_remaining > 0) {
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uint32_t will_write = MIN(bytes_remaining, DMA_BUF_SIZE);
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memcpy(emac->tx_buf[emac->cur_tx_desc], buf, will_write);
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openeth_tx_desc_t* desc_ptr = openeth_tx_desc(emac->cur_tx_desc);
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openeth_tx_desc_t *desc_ptr = openeth_tx_desc(emac->cur_tx_desc);
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openeth_tx_desc_t desc_val = *desc_ptr;
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desc_val.wr = (emac->cur_tx_desc == TX_BUF_COUNT - 1);
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desc_val.len = will_write;
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@ -265,7 +265,6 @@ static esp_err_t emac_opencores_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32
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{
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esp_err_t ret = ESP_OK;
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emac_opencores_t *emac = __containerof(mac, emac_opencores_t, parent);
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MAC_CHECK(buf && length, "can't set buf and length to null", err, ESP_ERR_INVALID_ARG);
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openeth_rx_desc_t *desc_ptr = openeth_rx_desc(emac->cur_rx_desc);
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openeth_rx_desc_t desc_val = *desc_ptr;
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@ -294,7 +293,7 @@ static esp_err_t emac_opencores_init(esp_eth_mac_t *mac)
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esp_eth_mediator_t *eth = emac->eth;
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MAC_CHECK(eth->on_state_changed(eth, ETH_STATE_LLINIT, NULL) == ESP_OK, "lowlevel init failed", err, ESP_FAIL);
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MAC_CHECK(esp_read_mac(emac->addr, ESP_MAC_ETH) == ESP_OK, "fetch ethernet mac address failed", err, ESP_FAIL);
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// Sanity check
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if (REG_READ(OPENETH_MODER_REG) != OPENETH_MODER_DEFAULT) {
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ESP_LOGE(TAG, "CONFIG_ETH_USE_OPENETH should only be used when running in QEMU.");
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@ -378,7 +377,7 @@ esp_eth_mac_t *esp_eth_mac_new_openeth(const eth_mac_config_t *config)
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emac->parent.set_promiscuous = emac_opencores_set_promiscuous;
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emac->parent.transmit = emac_opencores_transmit;
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emac->parent.receive = emac_opencores_receive;
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// Initialize the interrupt
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MAC_CHECK(esp_intr_alloc(OPENETH_INTR_SOURCE, ESP_INTR_FLAG_IRAM, emac_opencores_isr_handler,
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emac, &(emac->intr_hdl)) == ESP_OK,
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@ -438,11 +438,12 @@ uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal)
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return hal->tx_desc->TDES0.Own;
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}
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void emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length)
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uint32_t emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length)
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{
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/* Get the number of Tx buffers to use for the frame */
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uint32_t bufcount = 0;
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uint32_t lastlen = length;
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uint32_t sentout = 0;
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while (lastlen > CONFIG_ETH_DMA_BUFFER_SIZE) {
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lastlen -= CONFIG_ETH_DMA_BUFFER_SIZE;
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bufcount++;
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@ -452,6 +453,10 @@ void emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t len
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}
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/* A frame is transmitted in multiple descriptor */
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for (uint32_t i = 0; i < bufcount; i++) {
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/* Check if the descriptor is owned by the Ethernet DMA (when 1) or CPU (when 0) */
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if (hal->tx_desc->TDES0.Own != EMAC_DMADESC_OWNER_CPU) {
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goto err;
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}
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/* Clear FIRST and LAST segment bits */
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hal->tx_desc->TDES0.FirstSegment = 0;
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hal->tx_desc->TDES0.LastSegment = 0;
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@ -468,18 +473,22 @@ void emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t len
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hal->tx_desc->TDES1.TransmitBuffer1Size = lastlen;
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/* copy data from uplayer stack buffer */
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memcpy((void *)(hal->tx_desc->Buffer1Addr), buf + i * CONFIG_ETH_DMA_BUFFER_SIZE, lastlen);
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sentout += lastlen;
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} else {
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/* Program size */
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hal->tx_desc->TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
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/* copy data from uplayer stack buffer */
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memcpy((void *)(hal->tx_desc->Buffer1Addr), buf + i * CONFIG_ETH_DMA_BUFFER_SIZE, CONFIG_ETH_DMA_BUFFER_SIZE);
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sentout += CONFIG_ETH_DMA_BUFFER_SIZE;
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}
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/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
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hal->tx_desc->TDES0.Own = EMAC_DMADESC_OWNER_DMA;
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/* Point to next descriptor */
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hal->tx_desc = (eth_dma_tx_descriptor_t *)(hal->tx_desc->Buffer2NextDescAddr);
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}
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err:
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hal->dma_regs->dmatxpolldemand = 0;
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return sentout;
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}
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uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t size, uint32_t *frames_remain)
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@ -488,7 +497,9 @@ uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t
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eth_dma_rx_descriptor_t *first_desc = NULL;
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uint32_t iter = 0;
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uint32_t seg_count = 0;
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uint32_t len = 0;
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uint32_t ret_len = 0;
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uint32_t copy_len = 0;
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uint32_t write_len = 0;
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uint32_t frame_count = 0;
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first_desc = hal->rx_desc;
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@ -500,13 +511,9 @@ uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t
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/* Last segment in frame */
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if (desc_iter->RDES0.LastDescriptor) {
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/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
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len = desc_iter->RDES0.FrameLength - ETH_CRC_LENGTH;
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/* check if the buffer can store the whole frame */
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if (len > size) {
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/* return the real size that we want */
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/* user need to compare the return value to the size they prepared when this function returned */
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return len;
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}
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ret_len = desc_iter->RDES0.FrameLength - ETH_CRC_LENGTH;
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/* packets larger than expected will be truncated */
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copy_len = ret_len > size ? size : ret_len;
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/* update unhandled frame count */
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frame_count++;
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}
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@ -530,15 +537,16 @@ uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t
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}
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desc_iter = first_desc;
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for (iter = 0; iter < seg_count - 1; iter++) {
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write_len = copy_len < CONFIG_ETH_DMA_BUFFER_SIZE ? copy_len : CONFIG_ETH_DMA_BUFFER_SIZE;
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/* copy data to buffer */
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memcpy(buf + iter * CONFIG_ETH_DMA_BUFFER_SIZE,
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(void *)(desc_iter->Buffer1Addr), CONFIG_ETH_DMA_BUFFER_SIZE);
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memcpy(buf, (void *)(desc_iter->Buffer1Addr), write_len);
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buf += write_len;
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copy_len -= write_len;
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/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
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desc_iter->RDES0.Own = EMAC_DMADESC_OWNER_DMA;
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desc_iter = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
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}
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memcpy(buf + iter * CONFIG_ETH_DMA_BUFFER_SIZE,
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(void *)(desc_iter->Buffer1Addr), len % CONFIG_ETH_DMA_BUFFER_SIZE);
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memcpy(buf, (void *)(desc_iter->Buffer1Addr), copy_len);
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desc_iter->RDES0.Own = EMAC_DMADESC_OWNER_DMA;
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/* update rxdesc */
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hal->rx_desc = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
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@ -547,7 +555,7 @@ uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t
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frame_count--;
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}
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*frames_remain = frame_count;
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return len;
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return ret_len;
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}
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IRAM_ATTR void emac_hal_isr(void *arg)
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@ -242,6 +242,8 @@ typedef struct {
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#define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPSEGMENT 2 /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
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#define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPFULL 3 /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
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_Static_assert(sizeof(eth_dma_tx_descriptor_t) == 32, "eth_dma_tx_descriptor_t should occupy 32 bytes in memory");
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/**
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* @brief Ethernet DMA RX Descriptor
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*
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@ -328,6 +330,8 @@ typedef struct {
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#define EMAC_DMADESC_OWNER_CPU (0)
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#define EMAC_DMADESC_OWNER_DMA (1)
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_Static_assert(sizeof(eth_dma_rx_descriptor_t) == 32, "eth_dma_rx_descriptor_t should occupy 32 bytes in memory");
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typedef struct {
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emac_mac_dev_t *mac_regs;
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emac_dma_dev_t *dma_regs;
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@ -378,7 +382,7 @@ void emac_hal_stop(emac_hal_context_t *hal);
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uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal);
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void emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length);
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uint32_t emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length);
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uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t size, uint32_t *frames_remain);
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