kopia lustrzana https://github.com/espressif/esp-idf
SHA/RSA: moved all caps to soc_caps.h
Marius Vikhammer
bot
rodzic
f5939c9e68
commit
488f46acf5
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@ -22,7 +22,7 @@
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#include <stddef.h>
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#include <stdbool.h>
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#include "soc/sha_caps.h"
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#include "soc/soc_caps.h"
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#include "soc/lldesc.h"
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#include "hal/sha_types.h"
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@ -32,7 +32,7 @@
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#include "esp_log.h"
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#include "esp_attr.h"
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#include "bignum_impl.h"
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#include "soc/rsa_caps.h"
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#include "soc/soc_caps.h"
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#include <mbedtls/bignum.h>
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@ -26,7 +26,7 @@
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#if defined(MBEDTLS_SHA1_ALT)
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#include "hal/sha_types.h"
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#include "soc/sha_caps.h"
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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@ -26,7 +26,7 @@
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#if defined(MBEDTLS_SHA256_ALT)
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#include "hal/sha_types.h"
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#include "soc/sha_caps.h"
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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@ -26,7 +26,7 @@
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#if defined(MBEDTLS_SHA512_ALT)
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#include "hal/sha_types.h"
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#include "soc/sha_caps.h"
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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@ -44,7 +44,7 @@
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#include "sha/sha_dma.h"
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#include "hal/sha_hal.h"
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#include "soc/sha_caps.h"
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#include "soc/soc_caps.h"
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/cache.h"
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@ -16,7 +16,7 @@
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#include <stdio.h>
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#include <assert.h>
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#include "hal/sha_types.h"
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#include "soc/sha_caps.h"
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#include "soc/soc_caps.h"
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#include "esp_log.h"
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#include <mbedtls/sha1.h>
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@ -1,26 +0,0 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SOC_RSA_MAX_BIT_LEN (4096)
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#ifdef __cplusplus
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}
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#endif
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@ -1,34 +0,0 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SOC_SHA_SUPPORT_DMA (0)
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/* ESP32 style SHA engine, where multiple states can be stored in parallel */
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#define SOC_SHA_SUPPORT_PARALLEL_ENG (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA384 (1)
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#define SOC_SHA_SUPPORT_SHA512 (1)
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#ifdef __cplusplus
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}
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#endif
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@ -231,6 +231,22 @@
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* ESP32 style SHA engine, where multiple states can be stored in parallel */
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#define SOC_SHA_SUPPORT_PARALLEL_ENG (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA384 (1)
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#define SOC_SHA_SUPPORT_SHA512 (1)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (4096)
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/* ---------------------------- Compatibility ------------------------------- */
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#define SOC_CAN_SUPPORTED SOC_TWAI_SUPPORTED
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#define CAN_BRP_MIN SOC_TWAI_BRP_MIN
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@ -1,26 +0,0 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SOC_RSA_MAX_BIT_LEN (4096)
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#ifdef __cplusplus
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}
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#endif
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@ -1,54 +0,0 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Max amount of bytes in a single DMA operation is 4095,
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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#define SOC_SHA_SUPPORT_DMA (1)
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/* ESP32 style SHA engine, where multiple states can be stored in parallel */
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#define SOC_SHA_SUPPORT_PARALLEL_ENG (0)
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/* The SHA engine is able to resume hashing from a user */
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Has "crypto DMA", which is shared with AES */
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#define SOC_SHA_CRYPTO_DMA (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_SHA_GENERAL_DMA (0)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA384 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA512 (1)
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#define SOC_SHA_SUPPORT_SHA512_224 (1)
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#define SOC_SHA_SUPPORT_SHA512_256 (1)
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#define SOC_SHA_SUPPORT_SHA512_T (1)
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#ifdef __cplusplus
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}
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#endif
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@ -222,5 +222,43 @@
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/*-------------------------- USB CAPS ----------------------------------------*/
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#define SOC_USB_PERIPH_NUM 1
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* Max amount of bytes in a single DMA operation is 4095,
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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#define SOC_SHA_SUPPORT_DMA (1)
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/* The SHA engine is able to resume hashing from a user supplied context */
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Has "crypto DMA", which is shared with AES */
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#define SOC_SHA_CRYPTO_DMA (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA384 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA512 (1)
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#define SOC_SHA_SUPPORT_SHA512_224 (1)
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#define SOC_SHA_SUPPORT_SHA512_256 (1)
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#define SOC_SHA_SUPPORT_SHA512_T (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA384 (1)
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#define SOC_SHA_SUPPORT_SHA512 (1)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (4096)
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/* ---------------------------- Compatibility ------------------------------- */
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// No contents
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@ -1,26 +0,0 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SOC_RSA_MAX_BIT_LEN (4096)
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#ifdef __cplusplus
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}
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#endif
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@ -1,54 +0,0 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Max amount of bytes in a single DMA operation is 4095,
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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#define SOC_SHA_SUPPORT_DMA (1)
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/* ESP32 style SHA engine, where multiple states can be stored in parallel */
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#define SOC_SHA_SUPPORT_PARALLEL_ENG (0)
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/* The SHA engine is able to resume hashing from a user */
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Has "crypto DMA", which is shared with AES */
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#define SOC_SHA_CRYPTO_DMA (0)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_SHA_GENERAL_DMA (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA384 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA512 (1)
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#define SOC_SHA_SUPPORT_SHA512_224 (1)
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#define SOC_SHA_SUPPORT_SHA512_256 (1)
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#define SOC_SHA_SUPPORT_SHA512_T (1)
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#ifdef __cplusplus
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}
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#endif
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@ -93,6 +93,43 @@
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/*-------------------------- UART CAPS ---------------------------------------*/
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#include "uart_caps.h"
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* Max amount of bytes in a single DMA operation is 4095,
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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#define SOC_SHA_SUPPORT_DMA (1)
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/* The SHA engine is able to resume hashing from a user supplied context */
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_SHA_GENERAL_DMA (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA384 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA512 (1)
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#define SOC_SHA_SUPPORT_SHA512_224 (1)
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#define SOC_SHA_SUPPORT_SHA512_256 (1)
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#define SOC_SHA_SUPPORT_SHA512_T (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA384 (1)
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#define SOC_SHA_SUPPORT_SHA512 (1)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (4096)
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// Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically
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// Remove them when GDMA driver API is ready
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#define SOC_GDMA_M2M_DMA_CHANNEL (0)
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