2021-07-07 12:29:32 +00:00
|
|
|
module lvds_rx
|
|
|
|
(
|
2023-02-14 15:39:24 +00:00
|
|
|
input i_rst_b,
|
2021-07-07 12:29:32 +00:00
|
|
|
input i_ddr_clk,
|
|
|
|
input [1:0] i_ddr_data,
|
|
|
|
|
|
|
|
input i_fifo_full,
|
|
|
|
output o_fifo_write_clk,
|
|
|
|
output o_fifo_push,
|
2021-09-01 21:50:13 +00:00
|
|
|
output reg [31:0] o_fifo_data,
|
2023-02-14 15:39:24 +00:00
|
|
|
input i_sync_input,
|
2021-09-01 21:50:13 +00:00
|
|
|
output [1:0] o_debug_state );
|
2021-07-07 12:29:32 +00:00
|
|
|
|
|
|
|
// Internal FSM States
|
|
|
|
localparam
|
2021-09-01 21:50:13 +00:00
|
|
|
state_idle = 3'b00,
|
|
|
|
state_i_phase = 3'b01,
|
2021-09-03 08:19:28 +00:00
|
|
|
state_q_phase = 3'b11;
|
2021-09-01 21:50:13 +00:00
|
|
|
|
|
|
|
// Modem sync symbols
|
|
|
|
localparam
|
|
|
|
modem_i_sync = 3'b10,
|
|
|
|
modem_q_sync = 3'b01;
|
2021-07-07 12:29:32 +00:00
|
|
|
|
|
|
|
// Internal Registers
|
2021-09-01 21:50:13 +00:00
|
|
|
reg [1:0] r_state_if;
|
2021-07-07 12:29:32 +00:00
|
|
|
reg [2:0] r_phase_count;
|
2022-01-03 14:25:52 +00:00
|
|
|
reg r_cnt;
|
2023-02-14 15:39:24 +00:00
|
|
|
reg r_sync_input;
|
2021-07-07 12:29:32 +00:00
|
|
|
|
2021-09-01 21:50:13 +00:00
|
|
|
assign o_debug_state = r_state_if;
|
2021-07-07 12:29:32 +00:00
|
|
|
|
|
|
|
// Initial conditions
|
|
|
|
initial begin
|
|
|
|
r_state_if = state_idle;
|
|
|
|
r_phase_count = 3'b111;
|
|
|
|
end
|
|
|
|
|
|
|
|
// Global Assignments
|
|
|
|
assign o_fifo_write_clk = i_ddr_clk;
|
|
|
|
|
|
|
|
// Main Process
|
2023-02-14 15:39:24 +00:00
|
|
|
always @(posedge i_ddr_clk or negedge i_rst_b)
|
2021-07-07 12:29:32 +00:00
|
|
|
begin
|
2023-02-14 15:39:24 +00:00
|
|
|
if (i_rst_b == 1'b0) begin
|
|
|
|
r_state_if <= state_idle;
|
|
|
|
o_fifo_push <= 1'b0;
|
|
|
|
r_phase_count <= 3'b111;
|
|
|
|
r_cnt <= 0;
|
|
|
|
r_sync_input <= 1'b0;
|
2021-07-07 13:04:37 +00:00
|
|
|
end else begin
|
|
|
|
case (r_state_if)
|
|
|
|
state_idle: begin
|
2023-02-14 15:39:24 +00:00
|
|
|
if (i_ddr_data == modem_i_sync) begin
|
2021-07-07 13:04:37 +00:00
|
|
|
r_state_if <= state_i_phase;
|
2023-02-14 15:39:24 +00:00
|
|
|
o_fifo_data <= {30'b000000000000000000000000000000, i_ddr_data};
|
|
|
|
r_sync_input <= i_sync_input;
|
2021-07-07 13:04:37 +00:00
|
|
|
end
|
|
|
|
r_phase_count <= 3'b111;
|
2023-02-14 15:39:24 +00:00
|
|
|
o_fifo_push <= 1'b0;
|
2021-07-07 12:29:32 +00:00
|
|
|
end
|
|
|
|
|
2021-07-07 13:04:37 +00:00
|
|
|
state_i_phase: begin
|
|
|
|
if (r_phase_count == 3'b000) begin
|
2021-09-03 08:19:28 +00:00
|
|
|
if (i_ddr_data == modem_q_sync ) begin
|
2022-01-03 14:25:52 +00:00
|
|
|
r_phase_count <= 3'b110;
|
2021-09-01 21:50:13 +00:00
|
|
|
r_state_if <= state_q_phase;
|
|
|
|
end else begin
|
|
|
|
r_state_if <= state_idle;
|
|
|
|
end
|
2021-07-07 13:04:37 +00:00
|
|
|
end else begin
|
|
|
|
r_phase_count <= r_phase_count - 1;
|
|
|
|
end
|
2021-09-03 20:17:44 +00:00
|
|
|
|
2023-02-14 15:39:24 +00:00
|
|
|
o_fifo_push <= 1'b0;
|
|
|
|
o_fifo_data <= {o_fifo_data[29:0], i_ddr_data};
|
2021-07-07 12:29:32 +00:00
|
|
|
end
|
|
|
|
|
2021-07-07 13:04:37 +00:00
|
|
|
state_q_phase: begin
|
2021-09-01 21:50:13 +00:00
|
|
|
if (r_phase_count == 3'b000) begin
|
2023-02-14 15:39:24 +00:00
|
|
|
o_fifo_push <= ~i_fifo_full;
|
2021-07-07 13:04:37 +00:00
|
|
|
r_state_if <= state_idle;
|
2023-02-14 15:39:24 +00:00
|
|
|
o_fifo_data <= {o_fifo_data[29:0], i_ddr_data[1], r_sync_input};
|
2021-07-07 13:04:37 +00:00
|
|
|
end else begin
|
2023-02-14 15:39:24 +00:00
|
|
|
o_fifo_push <= 1'b0;
|
2021-07-07 13:04:37 +00:00
|
|
|
r_phase_count <= r_phase_count - 1;
|
2023-02-14 15:39:24 +00:00
|
|
|
o_fifo_data <= {o_fifo_data[29:0], i_ddr_data};
|
2021-07-07 13:04:37 +00:00
|
|
|
end
|
2023-02-14 15:39:24 +00:00
|
|
|
|
2021-07-07 12:29:32 +00:00
|
|
|
end
|
2021-07-07 13:04:37 +00:00
|
|
|
endcase
|
|
|
|
end
|
2023-02-14 15:39:24 +00:00
|
|
|
end
|
|
|
|
|
|
|
|
endmodule
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
module lvds_rx (input i_rst_b,
|
|
|
|
input i_ddr_clk,
|
|
|
|
input [1:0] i_ddr_data,
|
2021-07-07 13:04:37 +00:00
|
|
|
|
2023-02-14 15:39:24 +00:00
|
|
|
input i_fifo_full,
|
|
|
|
output o_fifo_write_clk,
|
|
|
|
output o_fifo_push,
|
|
|
|
output reg [31:0] o_fifo_data,
|
|
|
|
input i_sync_input,
|
|
|
|
output [1:0] o_debug_state );
|
|
|
|
|
|
|
|
|
|
|
|
// Internal FSM States
|
|
|
|
localparam
|
|
|
|
state_idle = 3'b00,
|
|
|
|
state_i_phase = 3'b01,
|
|
|
|
state_q_phase = 3'b11;
|
2021-07-07 13:04:37 +00:00
|
|
|
|
2023-02-14 15:39:24 +00:00
|
|
|
// Modem sync symbols
|
|
|
|
localparam
|
|
|
|
modem_i_sync = 3'b10,
|
|
|
|
modem_q_sync = 3'b01;
|
|
|
|
|
|
|
|
// Internal Registers
|
|
|
|
reg [1:0] r_state_if;
|
|
|
|
reg [3:0] r_phase_count;
|
|
|
|
|
|
|
|
assign o_debug_state = r_state_if;
|
|
|
|
|
|
|
|
// Initial conditions
|
|
|
|
initial begin
|
|
|
|
r_state_if = state_idle;
|
|
|
|
r_phase_count = 4'd15;
|
|
|
|
end
|
|
|
|
|
|
|
|
// Global Assignments
|
|
|
|
assign o_fifo_write_clk = i_ddr_clk;
|
|
|
|
|
|
|
|
// Main Process
|
|
|
|
// Data structure from the modem:
|
|
|
|
// [S'10'] [13'I] ['0'] [S'01'] [13'Q] ['0']
|
|
|
|
// Data structure with out sync 's'
|
|
|
|
// ['10'] [I] ['0'] ['01'] [Q] ['s']
|
|
|
|
always @(posedge i_ddr_clk or negedge i_rst_b)
|
|
|
|
begin
|
|
|
|
if (i_rst_b == 1'b0) begin
|
|
|
|
r_state_if <= state_idle;
|
|
|
|
r_phase_count <= 4'd15;
|
|
|
|
o_fifo_push <= 1'b0;
|
|
|
|
end else begin
|
|
|
|
case (r_state_if)
|
|
|
|
state_idle: begin
|
|
|
|
if (i_ddr_data == modem_i_sync ) begin
|
|
|
|
r_state_if <= state_i_phase;
|
|
|
|
end
|
|
|
|
r_phase_count <= 4'd15;
|
|
|
|
end
|
|
|
|
|
|
|
|
state_i_phase: begin
|
|
|
|
if (r_phase_count == 4'd8) begin
|
|
|
|
if (i_ddr_data == modem_q_sync ) begin
|
|
|
|
r_state_if <= state_q_phase;
|
|
|
|
end else begin
|
|
|
|
r_state_if <= state_idle;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
r_phase_count <= r_phase_count - 1;
|
|
|
|
end
|
|
|
|
|
|
|
|
state_q_phase: begin
|
|
|
|
if (r_phase_count == 4'd1) begin
|
|
|
|
r_state_if <= state_idle;
|
|
|
|
end
|
|
|
|
|
|
|
|
r_phase_count <= r_phase_count - 1;
|
|
|
|
end
|
|
|
|
endcase
|
|
|
|
|
|
|
|
o_fifo_data <= {o_fifo_data[29:0], i_ddr_data};
|
|
|
|
o_fifo_push <= r_phase_count == 4'd0 && ~i_fifo_full;
|
|
|
|
end
|
2021-07-07 12:29:32 +00:00
|
|
|
end
|
|
|
|
|
2023-02-14 15:39:24 +00:00
|
|
|
endmodule
|
|
|
|
*/
|