2021-07-07 12:29:32 +00:00
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module lvds_rx
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(
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input i_reset,
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input i_ddr_clk,
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input [1:0] i_ddr_data,
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input i_fifo_full,
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output o_fifo_write_clk,
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output o_fifo_push,
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output [31:0] o_fifo_data );
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// Internal FSM States
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localparam
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state_idle = 3'b000,
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state_i_phase = 3'b001,
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state_q_phase = 3'b010;
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// Internal Registers
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reg [2:0] r_state_if;
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reg [2:0] r_phase_count;
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reg [31:0] r_data;
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reg r_push;
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// Initial conditions
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initial begin
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r_state_if = state_idle;
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r_push = 1'b0;
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r_phase_count = 3'b111;
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r_data = 0;
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end
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// Global Assignments
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assign o_fifo_push = r_push;
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assign o_fifo_data = r_data;
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assign o_fifo_write_clk = i_ddr_clk;
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// Main Process
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always @(negedge i_ddr_clk)
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begin
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2021-07-07 13:04:37 +00:00
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if (i_reset) begin
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r_state_if = state_idle;
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r_push = 1'b0;
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r_phase_count = 3'b111;
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r_data = 0;
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end else begin
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case (r_state_if)
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state_idle: begin
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if (i_ddr_data == 2'b10 ) begin
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r_state_if <= state_i_phase;
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r_data <= 0; // may be redundant as we do a full loop
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end
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r_phase_count <= 3'b111;
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r_push <= 1'b0;
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2021-07-07 12:29:32 +00:00
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end
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2021-07-07 13:04:37 +00:00
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state_i_phase: begin
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if (r_phase_count == 3'b000) begin
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r_phase_count <= 3'b111;
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r_state_if <= state_q_phase;
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r_data <= {r_data[29:0], 2'b00};
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end else begin
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r_phase_count <= r_phase_count - 1;
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r_data <= {r_data[29:0], i_ddr_data};
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end
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2021-07-07 12:29:32 +00:00
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end
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2021-07-07 13:04:37 +00:00
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state_q_phase: begin
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if (r_phase_count == 3'b001) begin
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r_push <= ~i_fifo_full;
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r_phase_count <= 3'b000;
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r_state_if <= state_idle;
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end else begin
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r_phase_count <= r_phase_count - 1;
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end
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r_data <= {r_data[29:0], i_ddr_data};
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2021-07-07 12:29:32 +00:00
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end
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2021-07-07 13:04:37 +00:00
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endcase
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end
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2021-07-07 12:29:32 +00:00
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end
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endmodule // smi_ctrl
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