kopia lustrzana https://github.com/cariboulabs/cariboulite
added fifos - work in progress
meexmachina
rodzic
eb699bc363
commit
d61828c894
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@ -0,0 +1,150 @@
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/*
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* Copyright (c) 2012, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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* All rights reserved.
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*
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* Based on vga_fifo_dc.v in Richard Herveille's VGA/LCD core
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* Copyright (C) 2001 Richard Herveille <richard@asics.ws>
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*
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* Redistribution and use in source and non-source forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in non-source form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module dual_clock_fifo #(
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parameter ADDR_WIDTH = 8,
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parameter DATA_WIDTH = 16
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)
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(
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input wire wr_rst_i,
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input wire wr_clk_i,
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input wire wr_en_i,
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input wire [DATA_WIDTH-1:0] wr_data_i,
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input wire rd_rst_i,
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input wire rd_clk_i,
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input wire rd_en_i,
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output reg [DATA_WIDTH-1:0] rd_data_o,
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output reg full_o,
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output reg empty_o
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);
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reg [ADDR_WIDTH-1:0] wr_addr;
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reg [ADDR_WIDTH-1:0] wr_addr_gray;
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reg [ADDR_WIDTH-1:0] wr_addr_gray_rd;
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reg [ADDR_WIDTH-1:0] wr_addr_gray_rd_r;
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reg [ADDR_WIDTH-1:0] rd_addr;
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reg [ADDR_WIDTH-1:0] rd_addr_gray;
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reg [ADDR_WIDTH-1:0] rd_addr_gray_wr;
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reg [ADDR_WIDTH-1:0] rd_addr_gray_wr_r;
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function [ADDR_WIDTH-1:0] gray_conv;
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input [ADDR_WIDTH-1:0] in;
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begin
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gray_conv = {in[ADDR_WIDTH-1],
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in[ADDR_WIDTH-2:0] ^ in[ADDR_WIDTH-1:1]};
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end
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endfunction
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always @(posedge wr_clk_i) begin
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if (wr_rst_i) begin
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wr_addr <= 0;
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wr_addr_gray <= 0;
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end else if (wr_en_i) begin
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wr_addr <= wr_addr + 1'b1;
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wr_addr_gray <= gray_conv(wr_addr + 1'b1);
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end
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end
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// synchronize read address to write clock domain
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always @(posedge wr_clk_i) begin
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rd_addr_gray_wr <= rd_addr_gray;
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rd_addr_gray_wr_r <= rd_addr_gray_wr;
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end
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always @(posedge wr_clk_i)
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if (wr_rst_i)
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full_o <= 0;
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else if (wr_en_i)
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full_o <= gray_conv(wr_addr + 2) == rd_addr_gray_wr_r;
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else
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full_o <= full_o & (gray_conv(wr_addr + 1'b1) == rd_addr_gray_wr_r);
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always @(posedge rd_clk_i) begin
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if (rd_rst_i) begin
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rd_addr <= 0;
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rd_addr_gray <= 0;
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end else if (rd_en_i) begin
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rd_addr <= rd_addr + 1'b1;
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rd_addr_gray <= gray_conv(rd_addr + 1'b1);
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end
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end
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// synchronize write address to read clock domain
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always @(posedge rd_clk_i) begin
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wr_addr_gray_rd <= wr_addr_gray;
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wr_addr_gray_rd_r <= wr_addr_gray_rd;
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end
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always @(posedge rd_clk_i)
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if (rd_rst_i)
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empty_o <= 1'b1;
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else if (rd_en_i)
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empty_o <= gray_conv(rd_addr + 1) == wr_addr_gray_rd_r;
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else
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empty_o <= empty_o & (gray_conv(rd_addr) == wr_addr_gray_rd_r);
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// generate dual clocked memory
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SB_RAM256x16 ram256x16_i_inst (
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.RDATA(RDATA_c[15:0]),
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.RADDR(RADDR_c[7:0]),
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.RCLK(RCLK_c),
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.RCLKE(RCLKE_c),
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.RE(RE_c),
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.WADDR(WADDR_c[7:0]),
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.WCLK(WCLK_c),
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.WCLKE(WCLKE_c),
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.WDATA(WDATA_c[15:0]),
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.WE(WE_c),
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.MASK(MASK_c[15:0]) );
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SB_RAM256x16 ram256x16_q_inst (
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.RDATA(RDATA_c[15:0]),
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.RADDR(RADDR_c[7:0]),
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.RCLK(RCLK_c),
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.RCLKE(RCLKE_c),
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.RE(RE_c),
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.WADDR(WADDR_c[7:0]),
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.WCLK(WCLK_c),
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.WCLKE(WCLKE_c),
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.WDATA(WDATA_c[15:0]),
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.WE(WE_c),
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.MASK(MASK_c[15:0]) );
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reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
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always @(posedge rd_clk_i)
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if (rd_en_i)
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rd_data_o <= mem[rd_addr];
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always @(posedge wr_clk_i)
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if (wr_en_i)
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mem[wr_addr] <= wr_data_i;
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endmodule
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@ -38,38 +38,47 @@ module lvds_rx
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// Main Process
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always @(negedge i_ddr_clk)
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begin
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case (r_state_if)
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state_idle: begin
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if (i_ddr_data == 2'b10 ) begin
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r_state_if <= state_i_phase;
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r_data <= 0; // may be redundant as we do a full loop
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end
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r_phase_count <= 3'b111;
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r_push <= 1'b0;
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end
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state_i_phase: begin
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if (r_phase_count == 3'b000) begin
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if (i_reset) begin
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r_state_if = state_idle;
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r_push = 1'b0;
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r_phase_count = 3'b111;
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r_data = 0;
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end else begin
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case (r_state_if)
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state_idle: begin
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if (i_ddr_data == 2'b10 ) begin
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r_state_if <= state_i_phase;
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r_data <= 0; // may be redundant as we do a full loop
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end
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r_phase_count <= 3'b111;
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r_state_if <= state_q_phase;
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r_data <= {r_data[29:0], 2'b00};
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end else begin
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r_phase_count <= r_phase_count - 1;
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r_push <= 1'b0;
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end
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state_i_phase: begin
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if (r_phase_count == 3'b000) begin
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r_phase_count <= 3'b111;
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r_state_if <= state_q_phase;
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r_data <= {r_data[29:0], 2'b00};
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end else begin
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r_phase_count <= r_phase_count - 1;
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r_data <= {r_data[29:0], i_ddr_data};
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end
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end
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state_q_phase: begin
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if (r_phase_count == 3'b001) begin
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r_push <= ~i_fifo_full;
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r_phase_count <= 3'b000;
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r_state_if <= state_idle;
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end else begin
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r_phase_count <= r_phase_count - 1;
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end
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r_data <= {r_data[29:0], i_ddr_data};
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end
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end
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endcase
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end
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state_q_phase: begin
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if (r_phase_count == 3'b001) begin
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r_push <= ~i_fifo_full;
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r_phase_count <= 3'b000;
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r_state_if <= state_idle;
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end else begin
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r_phase_count <= r_phase_count - 1;
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end
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r_data <= {r_data[29:0], i_ddr_data};
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end
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endcase
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end
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endmodule // smi_ctrl
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6951
firmware/top.asc
6951
firmware/top.asc
Plik diff jest za duży
Load Diff
BIN
firmware/top.bin
BIN
firmware/top.bin
Plik binarny nie jest wyświetlany.
6838
firmware/top.json
6838
firmware/top.json
Plik diff jest za duży
Load Diff
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@ -3,6 +3,7 @@
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`include "io_ctrl.v"
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`include "smi_ctrl.v"
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`include "lvds_rx.v"
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`include "dual_clock_fifo.v"
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module top(
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input i_glob_clock,
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@ -71,7 +72,7 @@ module top(
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wire [3:0] w_cs;
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wire w_fetch;
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wire w_load;
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reg r_reset_b;
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reg r_reset;
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wire [7:0] w_tx_data_sys;
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wire [7:0] w_tx_data_io;
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@ -82,7 +83,7 @@ module top(
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//=========================================================================
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initial begin
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r_counter = 2'b00;
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r_reset_b = 1'b1;
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r_reset = 1'b0;
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end
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//=========================================================================
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@ -90,7 +91,7 @@ module top(
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//=========================================================================
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spi_if spi_if_ins
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(
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.i_rst_b (r_reset_b),
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.i_rst_b (r_reset),
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.i_sys_clk (w_clock_spi),
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.o_ioc (w_ioc),
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.o_data_in (w_rx_data),
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@ -237,14 +238,22 @@ module top(
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wire w_lvds_rx_09_d1; // 180 degree
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wire w_lvds_rx_24_d0; // 0 degree
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wire w_lvds_rx_24_d1; // 180 degree
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wire w_rx_09_fifo_full;
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wire w_rx_09_fifo_empty;
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wire w_rx_09_fifo_write_clk;
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wire w_rx_09_fifo_push;
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wire [31:0] w_rx_09_fifo_data;
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wire w_rx_09_fifo_pull;
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wire [31:0] w_rx_09_fifo_pulled_data;
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wire w_rx_24_fifo_full;
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wire w_rx_24_fifo_empty;
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wire w_rx_24_fifo_write_clk;
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wire w_rx_24_fifo_push;
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wire [31:0] w_rx_24_fifo_data;
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wire w_rx_24_fifo_pull;
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wire [31:0] w_rx_24_fifo_pulled_data;
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lvds_rx lvds_rx_09_inst
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(
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@ -257,6 +266,19 @@ module top(
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.o_fifo_data (w_rx_09_fifo_data)
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);
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dual_clock_fifo rx_09_fifo(
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.wr_rst_i (r_reset),
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.wr_clk_i (w_rx_09_fifo_write_clk),
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.wr_en_i (w_rx_09_fifo_push),
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.wr_data_i (w_rx_09_fifo_data),
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.rd_rst_i (r_reset),
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.rd_clk_i (w_clock_sys),
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.rd_en_i (w_rx_09_fifo_pull),
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.rd_data_o (w_rx_09_fifo_pulled_data),
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.full_o (w_rx_09_fifo_full),
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.empty_o (w_rx_09_fifo_empty)
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);
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lvds_rx lvds_rx_24_inst
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(
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.i_reset (r_reset),
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@ -268,10 +290,25 @@ module top(
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.o_fifo_data (w_rx_24_fifo_data)
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);
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dual_clock_fifo rx_24_fifo(
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.wr_rst_i (r_reset),
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.wr_clk_i (w_rx_24_fifo_write_clk),
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.wr_en_i (w_rx_24_fifo_push),
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.wr_data_i (w_rx_24_fifo_data),
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.rd_rst_i (r_reset),
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.rd_clk_i (w_clock_sys),
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.rd_en_i (w_rx_24_fifo_pull),
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.rd_data_o (w_rx_24_fifo_pulled_data),
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.full_o (w_rx_24_fifo_full),
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.empty_o (w_rx_24_fifo_empty)
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);
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// Testing - output the clock signal (positive and negative) to the PMOD
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assign io_pmod[0] = lvds_clock_buf;
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assign io_pmod[1] = w_rx_09_fifo_push;
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assign io_pmod[2] = w_rx_24_fifo_push;
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assign io_pmod[7:3] = w_rx_09_fifo_data[29:26];
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assign io_pmod[3] = w_rx_09_fifo_empty;
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assign io_pmod[4] = w_rx_24_fifo_empty;
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assign io_pmod[7:5] = w_rx_09_fifo_data[29:27];
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endmodule // top
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