62 Commity (a58cd2783789bc4ea3bceca82c088b749abdda3a)

Autor	SHA1	Wiadomość	Data
David Banks	c169996467	Calibrate clock based on VSYNC time ... Change-Id: I39dab208f2af217662921ffca6f5f8f69c7d6edb	2017-04-27 15:27:26 +01:00
David Banks	00e555bfdf	Automatic mode 7 support ... Change-Id: I93568cd3822e7e5aed9ff8b61d62eaa8a4fda193	2017-04-26 22:19:41 +01:00
David Banks	6d0263f280	Removed obsolete VSYNC logic from CPLD, pass through CSYNC to ARM ... Change-Id: I01c855dfd71e225bafbc5a03841581e9ff5c33cb	2017-04-26 18:15:47 +01:00
David Banks	4335d4e531	Early work on Mode 7 ... Change-Id: I0cea302fd7ea9ea8cb3649721185c2351b7084dc	2017-04-25 18:24:49 +01:00
David Banks	a0b2817ab1	Tweak sampling position by one notch ... Change-Id: I4dfdb5c424b584596b2beabb5df0e86e4ba393eb	2017-04-25 12:55:47 +01:00
David Banks	123ae936e1	Set all outputs to SLOW to reduce noise ... Change-Id: I8d28858c0972310a24c561575e341613278cfaa7	2017-04-25 12:55:20 +01:00
David Banks	cf17594877	Implemented vsync ... Change-Id: I35d7dc7a0184e147faa64fadf038752e7df467b9	2017-04-25 11:53:22 +01:00
David Banks	29d99e7110	VHDL: Adjust count when quad loaded ... Change-Id: Ieaf096aa6ffb574e470564ca70602ee92bde57ce	2017-04-25 10:06:38 +01:00
David Banks	6c519cdc29	VHDL: idle psync should be zero ... Change-Id: I3422fb75376be0c3a29e8f02b5019910e9c84614	2017-04-25 09:57:21 +01:00
David Banks	140b89d311	VHDL: Increased counter to 11 bits ... Change-Id: I269a63881ae52115f5989f72e85a536ed79f7e2f	2017-04-25 09:53:15 +01:00
David Banks	e3dbea5b30	VHDL: Updated .xise file ... Change-Id: I8d8fdbac96ed32383779f61b69c88800ee6bfcf9	2017-04-25 09:52:49 +01:00
David Banks	7fa14552bd	Initial version of VHDL ... Change-Id: I2fbdf73bc0feb8955a2b4b70856203e370cbad30	2017-04-24 20:21:18 +01:00