David Banks
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6d0263f280
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Removed obsolete VSYNC logic from CPLD, pass through CSYNC to ARM
Change-Id: I01c855dfd71e225bafbc5a03841581e9ff5c33cb
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2017-04-26 18:15:47 +01:00 |
David Banks
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4335d4e531
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Early work on Mode 7
Change-Id: I0cea302fd7ea9ea8cb3649721185c2351b7084dc
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2017-04-25 18:24:49 +01:00 |
David Banks
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a0b2817ab1
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Tweak sampling position by one notch
Change-Id: I4dfdb5c424b584596b2beabb5df0e86e4ba393eb
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2017-04-25 12:55:47 +01:00 |
David Banks
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cf17594877
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Implemented vsync
Change-Id: I35d7dc7a0184e147faa64fadf038752e7df467b9
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2017-04-25 11:53:22 +01:00 |
David Banks
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29d99e7110
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VHDL: Adjust count when quad loaded
Change-Id: Ieaf096aa6ffb574e470564ca70602ee92bde57ce
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2017-04-25 10:06:38 +01:00 |
David Banks
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6c519cdc29
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VHDL: idle psync should be zero
Change-Id: I3422fb75376be0c3a29e8f02b5019910e9c84614
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2017-04-25 09:57:21 +01:00 |
David Banks
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140b89d311
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VHDL: Increased counter to 11 bits
Change-Id: I269a63881ae52115f5989f72e85a536ed79f7e2f
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2017-04-25 09:53:15 +01:00 |
David Banks
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7fa14552bd
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Initial version of VHDL
Change-Id: I2fbdf73bc0feb8955a2b4b70856203e370cbad30
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2017-04-24 20:21:18 +01:00 |