kopia lustrzana https://github.com/conorpp/u2f-zero
784 wiersze
23 KiB
C
784 wiersze
23 KiB
C
//=========================================================
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// src/InitDevice.c: generated by Hardware Configurator
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//
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// This file will be regenerated when saving a document.
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// leave the sections inside the "$[...]" comment tags alone
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// or they will be overwritten!
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//=========================================================
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// USER INCLUDES
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#include <SI_EFM8UB1_Register_Enums.h>
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#include "InitDevice.h"
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// USER PROTOTYPES
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// USER FUNCTIONS
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// $[Library Includes]
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#include "efm8_usb.h"
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#include "descriptors.h"
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#include "usb_0.h"
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// [Library Includes]$
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//==============================================================================
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// enter_DefaultMode_from_RESET
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//==============================================================================
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void enter_DefaultMode_from_RESET(void) {
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// $[Config Calls]
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// Save the SFRPAGE
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uint8_t SFRPAGE_save = SFRPAGE;
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WDT_0_enter_DefaultMode_from_RESET();
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VREG_0_enter_DefaultMode_from_RESET();
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PORTS_0_enter_DefaultMode_from_RESET();
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PORTS_1_enter_DefaultMode_from_RESET();
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PBCFG_0_enter_DefaultMode_from_RESET();
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CIP51_0_enter_DefaultMode_from_RESET();
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CLOCK_0_enter_DefaultMode_from_RESET();
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TIMER01_0_enter_DefaultMode_from_RESET();
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TIMER16_2_enter_DefaultMode_from_RESET();
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TIMER16_3_enter_DefaultMode_from_RESET();
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TIMER_SETUP_0_enter_DefaultMode_from_RESET();
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PCA_0_enter_DefaultMode_from_RESET();
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PCACH_0_enter_DefaultMode_from_RESET();
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PCACH_1_enter_DefaultMode_from_RESET();
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PCACH_2_enter_DefaultMode_from_RESET();
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SMBUS_0_enter_DefaultMode_from_RESET();
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UART_0_enter_DefaultMode_from_RESET();
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INTERRUPT_0_enter_DefaultMode_from_RESET();
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USBLIB_0_enter_DefaultMode_from_RESET();
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// Restore the SFRPAGE
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SFRPAGE = SFRPAGE_save;
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// [Config Calls]$
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}
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//================================================================================
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// WDT_0_enter_DefaultMode_from_RESET
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//================================================================================
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static void WDT_0_enter_DefaultMode_from_RESET(void) {
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// $[WDTCN - Watchdog Timer Control]
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SFRPAGE = 0x00;
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// [WDTCN - Watchdog Timer Control]$
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}
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//================================================================================
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// VREG_0_enter_DefaultMode_from_RESET
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//================================================================================
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static void VREG_0_enter_DefaultMode_from_RESET(void) {
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// $[REG0CN - Voltage Regulator 0 Control]
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// [REG0CN - Voltage Regulator 0 Control]$
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// $[REG1CN - Voltage Regulator 1 Control]
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/*
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// Regulator is enabled
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// Regulator bias is disabled
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// The 5V regulator is in normal power mode. Normal mode is the highest
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// performance mode for the regulator
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*/
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SFRPAGE = 0x20;
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REG1CN = REG1CN_REG1ENB__ENABLED | REG1CN_BIASENB__DISABLED
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| REG1CN_SUSEN__NORMAL;
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// [REG1CN - Voltage Regulator 1 Control]$
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}
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//================================================================================
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// PORTS_0_enter_DefaultMode_from_RESET
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//================================================================================
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static void PORTS_0_enter_DefaultMode_from_RESET(void) {
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// $[P0 - Port 0 Pin Latch]
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// [P0 - Port 0 Pin Latch]$
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// $[P0MDOUT - Port 0 Output Mode]
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/*
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// P0.0 output is open-drain
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// P0.1 output is open-drain
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// P0.3 output is open-drain
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// P0.4 output is push-pull
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// P0.5 output is open-drain
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// P0.6 output is push-pull
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// P0.7 output is push-pull
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*/
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SFRPAGE = 0x00;
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P0MDOUT = P0MDOUT_B0__OPEN_DRAIN | P0MDOUT_B1__OPEN_DRAIN
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| P0MDOUT_B3__OPEN_DRAIN | P0MDOUT_B4__PUSH_PULL
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| P0MDOUT_B5__OPEN_DRAIN | P0MDOUT_B6__PUSH_PULL
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| P0MDOUT_B7__PUSH_PULL;
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// [P0MDOUT - Port 0 Output Mode]$
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// $[P0MDIN - Port 0 Input Mode]
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// [P0MDIN - Port 0 Input Mode]$
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// $[P0SKIP - Port 0 Skip]
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/*
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// P0.0 pin is not skipped by the crossbar
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// P0.1 pin is not skipped by the crossbar
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// P0.3 pin is skipped by the crossbar
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// P0.4 pin is not skipped by the crossbar
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// P0.5 pin is not skipped by the crossbar
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// P0.6 pin is skipped by the crossbar
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// P0.7 pin is not skipped by the crossbar
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*/
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P0SKIP = P0SKIP_B0__NOT_SKIPPED | P0SKIP_B1__NOT_SKIPPED
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|P0SKIP_B2__SKIPPED| P0SKIP_B3__SKIPPED | P0SKIP_B4__NOT_SKIPPED
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| P0SKIP_B5__NOT_SKIPPED | P0SKIP_B6__SKIPPED
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| P0SKIP_B7__NOT_SKIPPED;
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// [P0SKIP - Port 0 Skip]$
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// $[P0MASK - Port 0 Mask]
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// [P0MASK - Port 0 Mask]$
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// $[P0MAT - Port 0 Match]
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// [P0MAT - Port 0 Match]$
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}
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//================================================================================
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// PORTS_1_enter_DefaultMode_from_RESET
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//================================================================================
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static void PORTS_1_enter_DefaultMode_from_RESET(void) {
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// $[P1 - Port 1 Pin Latch]
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// [P1 - Port 1 Pin Latch]$
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// $[P1MDOUT - Port 1 Output Mode]
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/*
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// P1.0 output is push-pull
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// P1.1 output is push-pull
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// P1.2 output is open-drain
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// P1.3 output is open-drain
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// P1.4 output is open-drain
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// P1.5 output is push-pull
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// P1.6 output is push-pull
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*/
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P1MDOUT = P1MDOUT_B0__PUSH_PULL | P1MDOUT_B1__PUSH_PULL
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| P1MDOUT_B2__OPEN_DRAIN | P1MDOUT_B3__OPEN_DRAIN
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| P1MDOUT_B4__OPEN_DRAIN | P1MDOUT_B5__PUSH_PULL
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| P1MDOUT_B6__PUSH_PULL;
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// [P1MDOUT - Port 1 Output Mode]$
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// $[P1MDIN - Port 1 Input Mode]
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// [P1MDIN - Port 1 Input Mode]$
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// $[P1SKIP - Port 1 Skip]
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// [P1SKIP - Port 1 Skip]$
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// $[P1MASK - Port 1 Mask]
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// [P1MASK - Port 1 Mask]$
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// $[P1MAT - Port 1 Match]
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// [P1MAT - Port 1 Match]$
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}
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//================================================================================
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// PORTS_2_enter_DefaultMode_from_RESET
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//================================================================================
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static void PORTS_2_enter_DefaultMode_from_RESET(void) {
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// $[P2 - Port 2 Pin Latch]
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/*
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// B0 (Port 2 Bit 0 Latch) = HIGH (P2.0 is high. Set P2.0 to drive or
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// float high.)
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*/
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P2 = P2_B0__HIGH;
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// [P2 - Port 2 Pin Latch]$
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// $[P2MDOUT - Port 2 Output Mode]
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/*
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// B0 (Port 2 Bit 0 Output Mode) = OPEN_DRAIN (P2.0 output is open-
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// drain.)
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*/
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P2MDOUT = P2MDOUT_B0__OPEN_DRAIN;
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// [P2MDOUT - Port 2 Output Mode]$
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// $[P2MDIN - Port 2 Input Mode]
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/*
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// B0 (Port 2 Bit 0 Input Mode) = DIGITAL (P2.0 pin is configured for
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// digital mode.)
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*/
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SFRPAGE = 0x20;
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P2MDIN = P2MDIN_B0__DIGITAL;
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// [P2MDIN - Port 2 Input Mode]$
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// $[P2SKIP - Port 2 Skip]
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/*
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// B0 (Port 2 Bit 0 Skip) = SKIPPED (P2.0 pin is skipped by the
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// crossbar.)
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*/
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P2SKIP = P2SKIP_B0__SKIPPED;
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// [P2SKIP - Port 2 Skip]$
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// $[P2MASK - Port 2 Mask]
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/*
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// B0 (Port 2 Bit 0 Mask Value) = IGNORED (P2.0 pin logic value is
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// ignored and will not cause a port mismatch event.)
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*/
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P2MASK = P2MASK_B0__IGNORED;
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// [P2MASK - Port 2 Mask]$
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// $[P2MAT - Port 2 Match]
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/*
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// B0 (Port 2 Bit 0 Match Value) = HIGH (P2.0 pin logic value is compared
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// with logic HIGH.)
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*/
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P2MAT = P2MAT_B0__HIGH;
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// [P2MAT - Port 2 Match]$
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}
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//================================================================================
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// PBCFG_0_enter_DefaultMode_from_RESET
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//================================================================================
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static void PBCFG_0_enter_DefaultMode_from_RESET(void) {
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// $[XBR2 - Port I/O Crossbar 2]
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/*
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// Weak Pullups enabled
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// Crossbar enabled
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// UART1 I/O unavailable at Port pin
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// UART1 RTS1 unavailable at Port pin
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// UART1 CTS1 unavailable at Port pin
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*/
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XBR2 = XBR2_WEAKPUD__PULL_UPS_ENABLED | XBR2_XBARE__ENABLED
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| XBR2_URT1E__DISABLED | XBR2_URT1RTSE__DISABLED
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| XBR2_URT1CTSE__DISABLED;
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// [XBR2 - Port I/O Crossbar 2]$
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// $[PRTDRV - Port Drive Strength]
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// [PRTDRV - Port Drive Strength]$
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// $[XBR0 - Port I/O Crossbar 0]
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/*
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// UART0 TX0, RX0 routed to Port pins P0.4 and P0.5
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// SPI I/O unavailable at Port pins
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// SMBus 0 I/O routed to Port pins
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// CP0 unavailable at Port pin
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// Asynchronous CP0 unavailable at Port pin
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// CP1 unavailable at Port pin
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// Asynchronous CP1 unavailable at Port pin
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// SYSCLK unavailable at Port pin
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*/
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XBR0 = XBR0_URT0E__ENABLED | XBR0_SPI0E__DISABLED | XBR0_SMB0E__ENABLED
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| XBR0_CP0E__DISABLED | XBR0_CP0AE__DISABLED | XBR0_CP1E__DISABLED
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| XBR0_CP1AE__DISABLED | XBR0_SYSCKE__DISABLED;
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// [XBR0 - Port I/O Crossbar 0]$
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// $[XBR1 - Port I/O Crossbar 1]
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/*
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// CEX0, CEX1, CEX2 routed to Port pins
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// ECI unavailable at Port pin
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// T0 unavailable at Port pin
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// T1 unavailable at Port pin
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// T2 unavailable at Port pin
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*/
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XBR1 = XBR1_PCA0ME__CEX0_CEX1_CEX2 | XBR1_ECIE__DISABLED
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| XBR1_T0E__DISABLED | XBR1_T1E__DISABLED | XBR1_T2E__DISABLED;
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// [XBR1 - Port I/O Crossbar 1]$
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}
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//================================================================================
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// CIP51_0_enter_DefaultMode_from_RESET
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//================================================================================
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static void CIP51_0_enter_DefaultMode_from_RESET(void) {
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// $[PFE0CN - Prefetch Engine Control]
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/*
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// Enable the prefetch engine
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// SYSCLK < 50 MHz
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*/
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SFRPAGE = 0x10;
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PFE0CN = PFE0CN_PFEN__ENABLED | PFE0CN_FLRT__SYSCLK_BELOW_50_MHZ;
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// [PFE0CN - Prefetch Engine Control]$
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}
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//================================================================================
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// CLOCK_0_enter_DefaultMode_from_RESET
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//================================================================================
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static void CLOCK_0_enter_DefaultMode_from_RESET(void) {
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// $[HFOSC1 Setup]
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// Ensure SYSCLK is > 24 MHz before switching to HFOSC1
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SFRPAGE = 0x00;
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CLKSEL = CLKSEL_CLKSL__HFOSC0 | CLKSEL_CLKDIV__SYSCLK_DIV_1;
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while ((CLKSEL & CLKSEL_DIVRDY__BMASK) == CLKSEL_DIVRDY__NOT_READY)
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;
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// [HFOSC1 Setup]$
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// $[CLKSEL - Clock Select]
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/*
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// Clock derived from the Internal High Frequency Oscillator 1
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// SYSCLK is equal to selected clock source divided by 1
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*/
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CLKSEL = CLKSEL_CLKSL__HFOSC1 | CLKSEL_CLKDIV__SYSCLK_DIV_1;
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while ((CLKSEL & CLKSEL_DIVRDY__BMASK) == CLKSEL_DIVRDY__NOT_READY)
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;
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// [CLKSEL - Clock Select]$
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}
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//================================================================================
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// TIMER01_0_enter_DefaultMode_from_RESET
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//================================================================================
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static void TIMER01_0_enter_DefaultMode_from_RESET(void) {
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// $[Timer Initialization]
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//Save Timer Configuration
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uint8_t TCON_save;
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TCON_save = TCON;
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//Stop Timers
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TCON &= ~TCON_TR0__BMASK & ~TCON_TR1__BMASK;
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// [Timer Initialization]$
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// $[TH0 - Timer 0 High Byte]
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// [TH0 - Timer 0 High Byte]$
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// $[TL0 - Timer 0 Low Byte]
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// [TL0 - Timer 0 Low Byte]$
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// $[TH1 - Timer 1 High Byte]
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/*
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// Timer 1 High Byte = 0x30
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*/
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TH1 = (0x30 << TH1_TH1__SHIFT);
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// [TH1 - Timer 1 High Byte]$
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// $[TL1 - Timer 1 Low Byte]
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// [TL1 - Timer 1 Low Byte]$
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// $[Timer Restoration]
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//Restore Timer Configuration
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TCON |= (TCON_save & TCON_TR0__BMASK) | (TCON_save & TCON_TR1__BMASK);
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// [Timer Restoration]$
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}
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//================================================================================
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// TIMER16_2_enter_DefaultMode_from_RESET
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//================================================================================
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extern void TIMER16_2_enter_DefaultMode_from_RESET(void) {
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// $[Timer Initialization]
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// Save Timer Configuration
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uint8_t TMR2CN0_TR2_save;
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TMR2CN0_TR2_save = TMR2CN0 & TMR2CN0_TR2__BMASK;
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// Stop Timer
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TMR2CN0 &= ~(TMR2CN0_TR2__BMASK);
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// [Timer Initialization]$
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// $[TMR2CN1 - Timer 2 Control 1]
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// [TMR2CN1 - Timer 2 Control 1]$
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// $[TMR2CN0 - Timer 2 Control]
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// [TMR2CN0 - Timer 2 Control]$
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// $[TMR2H - Timer 2 High Byte]
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// [TMR2H - Timer 2 High Byte]$
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// $[TMR2L - Timer 2 Low Byte]
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// [TMR2L - Timer 2 Low Byte]$
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// $[TMR2RLH - Timer 2 Reload High Byte]
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/*
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// Timer 2 Reload High Byte = 0x44
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*/
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TMR2RLH = (0x44 << TMR2RLH_TMR2RLH__SHIFT);
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// [TMR2RLH - Timer 2 Reload High Byte]$
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// $[TMR2RLL - Timer 2 Reload Low Byte]
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/*
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// Timer 2 Reload Low Byte = 0x80
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*/
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TMR2RLL = (0x80 << TMR2RLL_TMR2RLL__SHIFT);
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// [TMR2RLL - Timer 2 Reload Low Byte]$
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// $[TMR2CN0]
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/*
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// Start Timer 2 running
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*/
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TMR2CN0 |= TMR2CN0_TR2__RUN;
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// [TMR2CN0]$
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// $[Timer Restoration]
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// Restore Timer Configuration
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TMR2CN0 |= TMR2CN0_TR2_save;
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// [Timer Restoration]$
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}
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//================================================================================
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// TIMER16_3_enter_DefaultMode_from_RESET
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//================================================================================
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extern void TIMER16_3_enter_DefaultMode_from_RESET(void) {
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// $[Timer Initialization]
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// Save Timer Configuration
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uint8_t TMR3CN0_TR3_save;
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TMR3CN0_TR3_save = TMR3CN0 & TMR3CN0_TR3__BMASK;
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// Stop Timer
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TMR3CN0 &= ~(TMR3CN0_TR3__BMASK);
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// [Timer Initialization]$
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// $[TMR3CN1 - Timer 3 Control 1]
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// [TMR3CN1 - Timer 3 Control 1]$
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// $[TMR3CN0 - Timer 3 Control]
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// [TMR3CN0 - Timer 3 Control]$
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// $[TMR3H - Timer 3 High Byte]
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// [TMR3H - Timer 3 High Byte]$
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// $[TMR3L - Timer 3 Low Byte]
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// [TMR3L - Timer 3 Low Byte]$
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// $[TMR3RLH - Timer 3 Reload High Byte]
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// [TMR3RLH - Timer 3 Reload High Byte]$
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// $[TMR3RLL - Timer 3 Reload Low Byte]
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// [TMR3RLL - Timer 3 Reload Low Byte]$
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// $[TMR3CN0]
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/*
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// Start Timer 3 running
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*/
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TMR3CN0 |= TMR3CN0_TR3__RUN;
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// [TMR3CN0]$
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// $[Timer Restoration]
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// Restore Timer Configuration
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TMR3CN0 |= TMR3CN0_TR3_save;
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// [Timer Restoration]$
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}
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//================================================================================
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// TIMER_SETUP_0_enter_DefaultMode_from_RESET
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//================================================================================
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extern void TIMER_SETUP_0_enter_DefaultMode_from_RESET(void) {
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// $[CKCON0 - Clock Control 0]
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/*
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// System clock divided by 12
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// Counter/Timer 0 uses the system clock
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// Timer 2 high byte uses the clock defined by T2XCLK in TMR2CN0
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// Timer 2 low byte uses the system clock
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// Timer 3 high byte uses the clock defined by T3XCLK in TMR3CN0
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// Timer 3 low byte uses the clock defined by T3XCLK in TMR3CN0
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// Timer 1 uses the system clock
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*/
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CKCON0 = CKCON0_SCA__SYSCLK_DIV_12 | CKCON0_T0M__SYSCLK
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| CKCON0_T2MH__EXTERNAL_CLOCK | CKCON0_T2ML__SYSCLK
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| CKCON0_T3MH__EXTERNAL_CLOCK | CKCON0_T3ML__EXTERNAL_CLOCK
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| CKCON0_T1M__SYSCLK;
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// [CKCON0 - Clock Control 0]$
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// $[CKCON1 - Clock Control 1]
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// [CKCON1 - Clock Control 1]$
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// $[TMOD - Timer 0/1 Mode]
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/*
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// Mode 1, 16-bit Counter/Timer
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// Mode 2, 8-bit Counter/Timer with Auto-Reload
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// Timer Mode. Timer 0 increments on the clock defined by T0M in the
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// CKCON0 register
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// Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level
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|
// Timer Mode. Timer 1 increments on the clock defined by T1M in the
|
|
// CKCON0 register
|
|
// Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level
|
|
*/
|
|
TMOD = TMOD_T0M__MODE1 | TMOD_T1M__MODE2 | TMOD_CT0__TIMER
|
|
| TMOD_GATE0__DISABLED | TMOD_CT1__TIMER | TMOD_GATE1__DISABLED;
|
|
// [TMOD - Timer 0/1 Mode]$
|
|
|
|
// $[TCON - Timer 0/1 Control]
|
|
/*
|
|
// Start Timer 1 running
|
|
*/
|
|
TCON |= TCON_TR1__RUN;
|
|
// [TCON - Timer 0/1 Control]$
|
|
|
|
}
|
|
|
|
//================================================================================
|
|
// SMBUS_0_enter_DefaultMode_from_RESET
|
|
//================================================================================
|
|
extern void SMBUS_0_enter_DefaultMode_from_RESET(void) {
|
|
// $[SMB0ADR - SMBus 0 Slave Address]
|
|
// [SMB0ADR - SMBus 0 Slave Address]$
|
|
|
|
// $[SMB0ADM - SMBus 0 Slave Address Mask]
|
|
// [SMB0ADM - SMBus 0 Slave Address Mask]$
|
|
|
|
// $[SMB0TC - SMBus 0 Timing and Pin Control]
|
|
// [SMB0TC - SMBus 0 Timing and Pin Control]$
|
|
|
|
// $[SMB0CF - SMBus 0 Configuration]
|
|
/*
|
|
// Timer 2 Low Byte Overflow
|
|
// Enable the SMBus module
|
|
// Enable bus free timeouts. The bus the bus will be considered free if
|
|
// SCL and SDA remain high for more than 10 SMBus clock source periods
|
|
// Enable SCL low timeouts
|
|
// Enable SDA extended setup and hold times
|
|
*/
|
|
SMB0CF |= SMB0CF_SMBCS__TIMER2_LOW | SMB0CF_ENSMB__ENABLED
|
|
| SMB0CF_SMBFTE__FREE_TO_ENABLED | SMB0CF_SMBTOE__SCL_TO_ENABLED
|
|
| SMB0CF_EXTHOLD__ENABLED;
|
|
// [SMB0CF - SMBus 0 Configuration]$
|
|
|
|
// $[SMB0FCN0 - SMBus0 FIFO Control 0]
|
|
// [SMB0FCN0 - SMBus0 FIFO Control 0]$
|
|
|
|
// $[SMB0RXLN - SMBus0 Receive Length Counter]
|
|
// [SMB0RXLN - SMBus0 Receive Length Counter]$
|
|
|
|
}
|
|
|
|
//================================================================================
|
|
// UART_0_enter_DefaultMode_from_RESET
|
|
//================================================================================
|
|
extern void UART_0_enter_DefaultMode_from_RESET(void) {
|
|
// $[SCON0 - UART0 Serial Port Control]
|
|
/*
|
|
// UART0 reception enabled
|
|
*/
|
|
SCON0 |= SCON0_REN__RECEIVE_ENABLED;
|
|
// [SCON0 - UART0 Serial Port Control]$
|
|
|
|
}
|
|
|
|
//================================================================================
|
|
// INTERRUPT_0_enter_DefaultMode_from_RESET
|
|
//================================================================================
|
|
extern void INTERRUPT_0_enter_DefaultMode_from_RESET(void) {
|
|
// $[EIE1 - Extended Interrupt Enable 1]
|
|
/*
|
|
// Disable ADC0 Conversion Complete interrupt
|
|
// Disable ADC0 Window Comparison interrupt
|
|
// Disable CP0 interrupts
|
|
// Disable CP1 interrupts
|
|
// Disable all Port Match interrupts
|
|
// Disable all PCA0 interrupts
|
|
// Enable interrupt requests generated by SMB0
|
|
// Enable interrupt requests generated by the TF3L or TF3H flags
|
|
*/
|
|
EIE1 = EIE1_EADC0__DISABLED | EIE1_EWADC0__DISABLED | EIE1_ECP0__DISABLED
|
|
| EIE1_ECP1__DISABLED | EIE1_EMAT__DISABLED | EIE1_EPCA0__DISABLED
|
|
| EIE1_ESMB0__ENABLED | EIE1_ET3__ENABLED;
|
|
// [EIE1 - Extended Interrupt Enable 1]$
|
|
|
|
// $[EIE2 - Extended Interrupt Enable 2]
|
|
// [EIE2 - Extended Interrupt Enable 2]$
|
|
|
|
// $[EIP1H - Extended Interrupt Priority 1 High]
|
|
// [EIP1H - Extended Interrupt Priority 1 High]$
|
|
|
|
// $[EIP1 - Extended Interrupt Priority 1 Low]
|
|
// [EIP1 - Extended Interrupt Priority 1 Low]$
|
|
|
|
// $[EIP2 - Extended Interrupt Priority 2]
|
|
// [EIP2 - Extended Interrupt Priority 2]$
|
|
|
|
// $[EIP2H - Extended Interrupt Priority 2 High]
|
|
// [EIP2H - Extended Interrupt Priority 2 High]$
|
|
|
|
// $[IE - Interrupt Enable]
|
|
/*
|
|
// Enable each interrupt according to its individual mask setting
|
|
// Disable external interrupt 0
|
|
// Disable external interrupt 1
|
|
// Disable all SPI0 interrupts
|
|
// Disable all Timer 0 interrupt
|
|
// Disable all Timer 1 interrupt
|
|
// Enable interrupt requests generated by the TF2L or TF2H flags
|
|
// Disable UART0 interrupt
|
|
*/
|
|
IE = IE_EA__ENABLED | IE_EX0__DISABLED | IE_EX1__DISABLED
|
|
| IE_ESPI0__DISABLED | IE_ET0__DISABLED | IE_ET1__DISABLED
|
|
| IE_ET2__ENABLED | IE_ES0__DISABLED;
|
|
// [IE - Interrupt Enable]$
|
|
|
|
// $[IP - Interrupt Priority]
|
|
// [IP - Interrupt Priority]$
|
|
|
|
// $[IPH - Interrupt Priority High]
|
|
// [IPH - Interrupt Priority High]$
|
|
|
|
}
|
|
|
|
//================================================================================
|
|
// USBLIB_0_enter_DefaultMode_from_RESET
|
|
//================================================================================
|
|
extern void USBLIB_0_enter_DefaultMode_from_RESET(void) {
|
|
// $[USBD Init]
|
|
USBD_Init (&initstruct);
|
|
// [USBD Init]$
|
|
|
|
}
|
|
|
|
extern void PCA_0_enter_DefaultMode_from_RESET(void) {
|
|
|
|
// $[PCA Off]
|
|
PCA0CN0_CR = PCA0CN0_CR__STOP;
|
|
// [PCA Off]$
|
|
|
|
// $[PCA0MD - PCA Mode]
|
|
// [PCA0MD - PCA Mode]$
|
|
|
|
// $[PCA0CENT - PCA Center Alignment Enable]
|
|
// [PCA0CENT - PCA Center Alignment Enable]$
|
|
|
|
// $[PCA0CLR - PCA Comparator Clear Control]
|
|
// [PCA0CLR - PCA Comparator Clear Control]$
|
|
|
|
// $[PCA0L - PCA Counter/Timer Low Byte]
|
|
// [PCA0L - PCA Counter/Timer Low Byte]$
|
|
|
|
// $[PCA0H - PCA Counter/Timer High Byte]
|
|
// [PCA0H - PCA Counter/Timer High Byte]$
|
|
|
|
// $[PCA0POL - PCA Output Polarity]
|
|
// [PCA0POL - PCA Output Polarity]$
|
|
|
|
// $[PCA0PWM - PCA PWM Configuration]
|
|
// [PCA0PWM - PCA PWM Configuration]$
|
|
|
|
// $[PCA On]
|
|
PCA0CN0_CR = PCA0CN0_CR__RUN;
|
|
// [PCA On]$
|
|
|
|
}
|
|
|
|
extern void PCACH_0_enter_DefaultMode_from_RESET(void) {
|
|
|
|
// $[PCA0 Settings Save]
|
|
// Select Capture/Compare register)
|
|
PCA0PWM &= ~PCA0PWM_ARSEL__BMASK;
|
|
// [PCA0 Settings Save]$
|
|
|
|
// $[PCA0CPM0 - PCA Channel 0 Capture/Compare Mode]
|
|
/*
|
|
// Disable negative edge capture
|
|
// Disable CCF0 interrupts
|
|
// Disable match function
|
|
// 8 to 11-bit PWM selected
|
|
// Disable positive edge capture
|
|
// Enable comparator function
|
|
// Enable PWM function
|
|
// Disable toggle function
|
|
*/
|
|
PCA0CPM0 = PCA0CPM0_CAPN__DISABLED | PCA0CPM0_ECCF__DISABLED
|
|
| PCA0CPM0_MAT__DISABLED | PCA0CPM0_PWM16__8_BIT
|
|
| PCA0CPM0_CAPP__DISABLED | PCA0CPM0_ECOM__ENABLED
|
|
| PCA0CPM0_PWM__ENABLED | PCA0CPM0_TOG__DISABLED;
|
|
// [PCA0CPM0 - PCA Channel 0 Capture/Compare Mode]$
|
|
|
|
// $[PCA0CPL0 - PCA Channel 0 Capture Module Low Byte]
|
|
/*
|
|
// PCA Channel 0 Capture Module Low Byte = 0x96
|
|
*/
|
|
PCA0CPL0 = (0x96 << PCA0CPL0_PCA0CPL0__SHIFT);
|
|
// [PCA0CPL0 - PCA Channel 0 Capture Module Low Byte]$
|
|
|
|
// $[PCA0CPH0 - PCA Channel 0 Capture Module High Byte]
|
|
/*
|
|
// PCA Channel 0 Capture Module High Byte = 0x96
|
|
*/
|
|
PCA0CPH0 = (0x96 << PCA0CPH0_PCA0CPH0__SHIFT);
|
|
// [PCA0CPH0 - PCA Channel 0 Capture Module High Byte]$
|
|
|
|
// $[Auto-reload]
|
|
// [Auto-reload]$
|
|
|
|
// $[PCA0 Settings Restore]
|
|
// [PCA0 Settings Restore]$
|
|
|
|
}
|
|
|
|
extern void PCACH_1_enter_DefaultMode_from_RESET(void) {
|
|
|
|
// $[PCA0 Settings Save]
|
|
// Select Capture/Compare register)
|
|
PCA0PWM &= ~PCA0PWM_ARSEL__BMASK;
|
|
// [PCA0 Settings Save]$
|
|
|
|
// $[PCA0CPM1 - PCA Channel 1 Capture/Compare Mode]
|
|
/*
|
|
// Disable negative edge capture
|
|
// Disable CCF1 interrupts
|
|
// Disable match function
|
|
// 8 to 11-bit PWM selected
|
|
// Disable positive edge capture
|
|
// Enable comparator function
|
|
// Enable PWM function
|
|
// Disable toggle function
|
|
*/
|
|
PCA0CPM1 = PCA0CPM1_CAPN__DISABLED | PCA0CPM1_ECCF__DISABLED
|
|
| PCA0CPM1_MAT__DISABLED | PCA0CPM1_PWM16__8_BIT
|
|
| PCA0CPM1_CAPP__DISABLED | PCA0CPM1_ECOM__ENABLED
|
|
| PCA0CPM1_PWM__ENABLED | PCA0CPM1_TOG__DISABLED;
|
|
// [PCA0CPM1 - PCA Channel 1 Capture/Compare Mode]$
|
|
|
|
// $[PCA0CPL1 - PCA Channel 1 Capture Module Low Byte]
|
|
/*
|
|
// PCA Channel 1 Capture Module Low Byte = 0x96
|
|
*/
|
|
PCA0CPL1 = (0x96 << PCA0CPL1_PCA0CPL1__SHIFT);
|
|
// [PCA0CPL1 - PCA Channel 1 Capture Module Low Byte]$
|
|
|
|
// $[PCA0CPH1 - PCA Channel 1 Capture Module High Byte]
|
|
/*
|
|
// PCA Channel 1 Capture Module High Byte = 0x96
|
|
*/
|
|
PCA0CPH1 = (0x96 << PCA0CPH1_PCA0CPH1__SHIFT);
|
|
// [PCA0CPH1 - PCA Channel 1 Capture Module High Byte]$
|
|
|
|
// $[Auto-reload]
|
|
// [Auto-reload]$
|
|
|
|
// $[PCA0 Settings Restore]
|
|
// [PCA0 Settings Restore]$
|
|
|
|
}
|
|
|
|
extern void PCACH_2_enter_DefaultMode_from_RESET(void) {
|
|
|
|
// $[PCA0 Settings Save]
|
|
// Select Capture/Compare register)
|
|
PCA0PWM &= ~PCA0PWM_ARSEL__BMASK;
|
|
// [PCA0 Settings Save]$
|
|
|
|
// $[PCA0CPM2 - PCA Channel 2 Capture/Compare Mode]
|
|
/*
|
|
// Disable negative edge capture
|
|
// Disable CCF2 interrupts
|
|
// Disable match function
|
|
// 8 to 11-bit PWM selected
|
|
// Disable positive edge capture
|
|
// Enable comparator function
|
|
// Enable PWM function
|
|
// Disable toggle function
|
|
*/
|
|
PCA0CPM2 = PCA0CPM2_CAPN__DISABLED | PCA0CPM2_ECCF__DISABLED
|
|
| PCA0CPM2_MAT__DISABLED | PCA0CPM2_PWM16__8_BIT
|
|
| PCA0CPM2_CAPP__DISABLED | PCA0CPM2_ECOM__ENABLED
|
|
| PCA0CPM2_PWM__ENABLED | PCA0CPM2_TOG__DISABLED;
|
|
// [PCA0CPM2 - PCA Channel 2 Capture/Compare Mode]$
|
|
|
|
// $[PCA0CPL2 - PCA Channel 2 Capture Module Low Byte]
|
|
/*
|
|
// PCA Channel 2 Capture Module Low Byte = 0x96
|
|
*/
|
|
PCA0CPL2 = (0x96 << PCA0CPL2_PCA0CPL2__SHIFT);
|
|
// [PCA0CPL2 - PCA Channel 2 Capture Module Low Byte]$
|
|
|
|
// $[PCA0CPH2 - PCA Channel 2 Capture Module High Byte]
|
|
/*
|
|
// PCA Channel 2 Capture Module High Byte = 0x96
|
|
*/
|
|
PCA0CPH2 = (0x96 << PCA0CPH2_PCA0CPH2__SHIFT);
|
|
// [PCA0CPH2 - PCA Channel 2 Capture Module High Byte]$
|
|
|
|
// $[Auto-reload]
|
|
// [Auto-reload]$
|
|
|
|
// $[PCA0 Settings Restore]
|
|
// [PCA0 Settings Restore]$
|
|
|
|
}
|