//=========================================================
// src/InitDevice.c: generated by Hardware Configurator
//
// This file will be regenerated when saving a document.
// leave the sections inside the "$[...]" comment tags alone
// or they will be overwritten!
//=========================================================

// USER INCLUDES
#include <SI_EFM8UB1_Register_Enums.h>
#include "InitDevice.h"

// USER PROTOTYPES
// USER FUNCTIONS

// $[Library Includes]
#include "efm8_usb.h"
#include "descriptors.h"
#include "usb_0.h"
// [Library Includes]$

//==============================================================================
// enter_DefaultMode_from_RESET
//==============================================================================
void enter_DefaultMode_from_RESET(void) {
	// $[Config Calls]
	// Save the SFRPAGE
	uint8_t SFRPAGE_save = SFRPAGE;
	WDT_0_enter_DefaultMode_from_RESET();
	VREG_0_enter_DefaultMode_from_RESET();
	PORTS_0_enter_DefaultMode_from_RESET();
	PORTS_1_enter_DefaultMode_from_RESET();
	PBCFG_0_enter_DefaultMode_from_RESET();
	CIP51_0_enter_DefaultMode_from_RESET();
	CLOCK_0_enter_DefaultMode_from_RESET();
	TIMER01_0_enter_DefaultMode_from_RESET();
	TIMER16_2_enter_DefaultMode_from_RESET();
	TIMER16_3_enter_DefaultMode_from_RESET();
	TIMER_SETUP_0_enter_DefaultMode_from_RESET();
	PCA_0_enter_DefaultMode_from_RESET();
	PCACH_0_enter_DefaultMode_from_RESET();
	PCACH_1_enter_DefaultMode_from_RESET();
	PCACH_2_enter_DefaultMode_from_RESET();
	SMBUS_0_enter_DefaultMode_from_RESET();
	UART_0_enter_DefaultMode_from_RESET();
	INTERRUPT_0_enter_DefaultMode_from_RESET();
	USBLIB_0_enter_DefaultMode_from_RESET();
	// Restore the SFRPAGE
	SFRPAGE = SFRPAGE_save;
	// [Config Calls]$

}

//================================================================================
// WDT_0_enter_DefaultMode_from_RESET
//================================================================================
static void WDT_0_enter_DefaultMode_from_RESET(void) {
	// $[WDTCN - Watchdog Timer Control]
	SFRPAGE = 0x00;
	// [WDTCN - Watchdog Timer Control]$

}

//================================================================================
// VREG_0_enter_DefaultMode_from_RESET
//================================================================================
static void VREG_0_enter_DefaultMode_from_RESET(void) {
	// $[REG0CN - Voltage Regulator 0 Control]
	// [REG0CN - Voltage Regulator 0 Control]$

	// $[REG1CN - Voltage Regulator 1 Control]
	/*
	 // Regulator is enabled
	 // Regulator bias is disabled
	 // The 5V regulator is in normal power mode. Normal mode is the highest
	 //     performance mode for the regulator
	 */
	SFRPAGE = 0x20;
	REG1CN = REG1CN_REG1ENB__ENABLED | REG1CN_BIASENB__DISABLED
			| REG1CN_SUSEN__NORMAL;
	// [REG1CN - Voltage Regulator 1 Control]$

}

//================================================================================
// PORTS_0_enter_DefaultMode_from_RESET
//================================================================================
static void PORTS_0_enter_DefaultMode_from_RESET(void) {
	// $[P0 - Port 0 Pin Latch]
	// [P0 - Port 0 Pin Latch]$

	// $[P0MDOUT - Port 0 Output Mode]
	/*
	 // P0.0 output is open-drain
	 // P0.1 output is open-drain
	 // P0.3 output is open-drain
	 // P0.4 output is push-pull
	 // P0.5 output is open-drain
	 // P0.6 output is push-pull
	 // P0.7 output is push-pull
	 */
	SFRPAGE = 0x00;
	P0MDOUT = P0MDOUT_B0__OPEN_DRAIN | P0MDOUT_B1__OPEN_DRAIN
			| P0MDOUT_B3__OPEN_DRAIN | P0MDOUT_B4__PUSH_PULL
			| P0MDOUT_B5__OPEN_DRAIN | P0MDOUT_B6__PUSH_PULL
			| P0MDOUT_B7__PUSH_PULL;
	// [P0MDOUT - Port 0 Output Mode]$

	// $[P0MDIN - Port 0 Input Mode]
	// [P0MDIN - Port 0 Input Mode]$

	// $[P0SKIP - Port 0 Skip]
	/*
	 // P0.0 pin is not skipped by the crossbar
	 // P0.1 pin is not skipped by the crossbar
	 // P0.3 pin is skipped by the crossbar
	 // P0.4 pin is not skipped by the crossbar
	 // P0.5 pin is not skipped by the crossbar
	 // P0.6 pin is skipped by the crossbar
	 // P0.7 pin is not skipped by the crossbar
	 */
	P0SKIP = P0SKIP_B0__NOT_SKIPPED | P0SKIP_B1__NOT_SKIPPED
			|P0SKIP_B2__SKIPPED| P0SKIP_B3__SKIPPED | P0SKIP_B4__NOT_SKIPPED
			| P0SKIP_B5__NOT_SKIPPED | P0SKIP_B6__SKIPPED
			| P0SKIP_B7__NOT_SKIPPED;
	// [P0SKIP - Port 0 Skip]$

	// $[P0MASK - Port 0 Mask]
	// [P0MASK - Port 0 Mask]$

	// $[P0MAT - Port 0 Match]
	// [P0MAT - Port 0 Match]$

}

//================================================================================
// PORTS_1_enter_DefaultMode_from_RESET
//================================================================================
static void PORTS_1_enter_DefaultMode_from_RESET(void) {
	// $[P1 - Port 1 Pin Latch]
	// [P1 - Port 1 Pin Latch]$

	// $[P1MDOUT - Port 1 Output Mode]
	/*
	 // P1.0 output is push-pull
	 // P1.1 output is push-pull
	 // P1.2 output is open-drain
	 // P1.3 output is open-drain
	 // P1.4 output is open-drain
	 // P1.5 output is push-pull
	 // P1.6 output is push-pull
	 */
	P1MDOUT = P1MDOUT_B0__PUSH_PULL | P1MDOUT_B1__PUSH_PULL
			| P1MDOUT_B2__OPEN_DRAIN | P1MDOUT_B3__OPEN_DRAIN
			| P1MDOUT_B4__OPEN_DRAIN | P1MDOUT_B5__PUSH_PULL
			| P1MDOUT_B6__PUSH_PULL;
	// [P1MDOUT - Port 1 Output Mode]$

	// $[P1MDIN - Port 1 Input Mode]
	// [P1MDIN - Port 1 Input Mode]$

	// $[P1SKIP - Port 1 Skip]
	// [P1SKIP - Port 1 Skip]$

	// $[P1MASK - Port 1 Mask]
	// [P1MASK - Port 1 Mask]$

	// $[P1MAT - Port 1 Match]
	// [P1MAT - Port 1 Match]$

}

//================================================================================
// PORTS_2_enter_DefaultMode_from_RESET
//================================================================================
static void PORTS_2_enter_DefaultMode_from_RESET(void) {
	// $[P2 - Port 2 Pin Latch]
	/*
	 // B0 (Port 2 Bit 0 Latch) = HIGH (P2.0 is high. Set P2.0 to drive or
	 //     float high.)
	 */
	P2 = P2_B0__HIGH;
	// [P2 - Port 2 Pin Latch]$

	// $[P2MDOUT - Port 2 Output Mode]
	/*
	 // B0 (Port 2 Bit 0 Output Mode) = OPEN_DRAIN (P2.0 output is open-
	 //     drain.)
	 */
	P2MDOUT = P2MDOUT_B0__OPEN_DRAIN;
	// [P2MDOUT - Port 2 Output Mode]$

	// $[P2MDIN - Port 2 Input Mode]
	/*
	 // B0 (Port 2 Bit 0 Input Mode) = DIGITAL (P2.0 pin is configured for
	 //     digital mode.)
	 */
	SFRPAGE = 0x20;
	P2MDIN = P2MDIN_B0__DIGITAL;
	// [P2MDIN - Port 2 Input Mode]$

	// $[P2SKIP - Port 2 Skip]
	/*
	 // B0 (Port 2 Bit 0 Skip) = SKIPPED (P2.0 pin is skipped by the
	 //     crossbar.)
	 */
	P2SKIP = P2SKIP_B0__SKIPPED;
	// [P2SKIP - Port 2 Skip]$

	// $[P2MASK - Port 2 Mask]
	/*
	 // B0 (Port 2 Bit 0 Mask Value) = IGNORED (P2.0 pin logic value is
	 //     ignored and will not cause a port mismatch event.)
	 */
	P2MASK = P2MASK_B0__IGNORED;
	// [P2MASK - Port 2 Mask]$

	// $[P2MAT - Port 2 Match]
	/*
	 // B0 (Port 2 Bit 0 Match Value) = HIGH (P2.0 pin logic value is compared
	 //     with logic HIGH.)
	 */
	P2MAT = P2MAT_B0__HIGH;
	// [P2MAT - Port 2 Match]$

}

//================================================================================
// PBCFG_0_enter_DefaultMode_from_RESET
//================================================================================
static void PBCFG_0_enter_DefaultMode_from_RESET(void) {
	// $[XBR2 - Port I/O Crossbar 2]
	/*
	 // Weak Pullups enabled 
	 // Crossbar enabled
	 // UART1 I/O unavailable at Port pin
	 // UART1 RTS1 unavailable at Port pin
	 // UART1 CTS1 unavailable at Port pin
	 */
	XBR2 = XBR2_WEAKPUD__PULL_UPS_ENABLED | XBR2_XBARE__ENABLED
			| XBR2_URT1E__DISABLED | XBR2_URT1RTSE__DISABLED
			| XBR2_URT1CTSE__DISABLED;
	// [XBR2 - Port I/O Crossbar 2]$

	// $[PRTDRV - Port Drive Strength]
	// [PRTDRV - Port Drive Strength]$

	// $[XBR0 - Port I/O Crossbar 0]
	/*
	 // UART0 TX0, RX0 routed to Port pins P0.4 and P0.5
	 // SPI I/O unavailable at Port pins
	 // SMBus 0 I/O routed to Port pins
	 // CP0 unavailable at Port pin
	 // Asynchronous CP0 unavailable at Port pin
	 // CP1 unavailable at Port pin
	 // Asynchronous CP1 unavailable at Port pin
	 // SYSCLK unavailable at Port pin
	 */
	XBR0 = XBR0_URT0E__ENABLED | XBR0_SPI0E__DISABLED | XBR0_SMB0E__ENABLED
			| XBR0_CP0E__DISABLED | XBR0_CP0AE__DISABLED | XBR0_CP1E__DISABLED
			| XBR0_CP1AE__DISABLED | XBR0_SYSCKE__DISABLED;
	// [XBR0 - Port I/O Crossbar 0]$

	// $[XBR1 - Port I/O Crossbar 1]
	/*
	 // CEX0, CEX1, CEX2 routed to Port pins
	 // ECI unavailable at Port pin
	 // T0 unavailable at Port pin
	 // T1 unavailable at Port pin
	 // T2 unavailable at Port pin
	 */
	XBR1 = XBR1_PCA0ME__CEX0_CEX1_CEX2 | XBR1_ECIE__DISABLED
			| XBR1_T0E__DISABLED | XBR1_T1E__DISABLED | XBR1_T2E__DISABLED;
	// [XBR1 - Port I/O Crossbar 1]$

}

//================================================================================
// CIP51_0_enter_DefaultMode_from_RESET
//================================================================================
static void CIP51_0_enter_DefaultMode_from_RESET(void) {
	// $[PFE0CN - Prefetch Engine Control]
	/*
	 // Enable the prefetch engine 
	 // SYSCLK < 50 MHz
	 */
	SFRPAGE = 0x10;
	PFE0CN = PFE0CN_PFEN__ENABLED | PFE0CN_FLRT__SYSCLK_BELOW_50_MHZ;
	// [PFE0CN - Prefetch Engine Control]$

}

//================================================================================
// CLOCK_0_enter_DefaultMode_from_RESET
//================================================================================
static void CLOCK_0_enter_DefaultMode_from_RESET(void) {
	// $[HFOSC1 Setup]
	// Ensure SYSCLK is > 24 MHz before switching to HFOSC1
	SFRPAGE = 0x00;
	CLKSEL = CLKSEL_CLKSL__HFOSC0 | CLKSEL_CLKDIV__SYSCLK_DIV_1;
	while ((CLKSEL & CLKSEL_DIVRDY__BMASK) == CLKSEL_DIVRDY__NOT_READY)
		;
	// [HFOSC1 Setup]$

	// $[CLKSEL - Clock Select]
	/*
	 // Clock derived from the Internal High Frequency Oscillator 1
	 // SYSCLK is equal to selected clock source divided by 1
	 */
	CLKSEL = CLKSEL_CLKSL__HFOSC1 | CLKSEL_CLKDIV__SYSCLK_DIV_1;
	while ((CLKSEL & CLKSEL_DIVRDY__BMASK) == CLKSEL_DIVRDY__NOT_READY)
		;
	// [CLKSEL - Clock Select]$

}

//================================================================================
// TIMER01_0_enter_DefaultMode_from_RESET
//================================================================================
static void TIMER01_0_enter_DefaultMode_from_RESET(void) {
	// $[Timer Initialization]
	//Save Timer Configuration
	uint8_t TCON_save;
	TCON_save = TCON;
	//Stop Timers
	TCON &= ~TCON_TR0__BMASK & ~TCON_TR1__BMASK;

	// [Timer Initialization]$

	// $[TH0 - Timer 0 High Byte]
	// [TH0 - Timer 0 High Byte]$

	// $[TL0 - Timer 0 Low Byte]
	// [TL0 - Timer 0 Low Byte]$

	// $[TH1 - Timer 1 High Byte]
	/*
	 // Timer 1 High Byte = 0x30
	 */
	TH1 = (0x30 << TH1_TH1__SHIFT);
	// [TH1 - Timer 1 High Byte]$

	// $[TL1 - Timer 1 Low Byte]
	// [TL1 - Timer 1 Low Byte]$

	// $[Timer Restoration]
	//Restore Timer Configuration
	TCON |= (TCON_save & TCON_TR0__BMASK) | (TCON_save & TCON_TR1__BMASK);

	// [Timer Restoration]$

}

//================================================================================
// TIMER16_2_enter_DefaultMode_from_RESET
//================================================================================
extern void TIMER16_2_enter_DefaultMode_from_RESET(void) {
	// $[Timer Initialization]
	// Save Timer Configuration
	uint8_t TMR2CN0_TR2_save;
	TMR2CN0_TR2_save = TMR2CN0 & TMR2CN0_TR2__BMASK;
	// Stop Timer
	TMR2CN0 &= ~(TMR2CN0_TR2__BMASK);
	// [Timer Initialization]$

	// $[TMR2CN1 - Timer 2 Control 1]
	// [TMR2CN1 - Timer 2 Control 1]$

	// $[TMR2CN0 - Timer 2 Control]
	// [TMR2CN0 - Timer 2 Control]$

	// $[TMR2H - Timer 2 High Byte]
	// [TMR2H - Timer 2 High Byte]$

	// $[TMR2L - Timer 2 Low Byte]
	// [TMR2L - Timer 2 Low Byte]$

	// $[TMR2RLH - Timer 2 Reload High Byte]
	/*
	 // Timer 2 Reload High Byte = 0x44
	 */
	TMR2RLH = (0x44 << TMR2RLH_TMR2RLH__SHIFT);
	// [TMR2RLH - Timer 2 Reload High Byte]$

	// $[TMR2RLL - Timer 2 Reload Low Byte]
	/*
	 // Timer 2 Reload Low Byte = 0x80
	 */
	TMR2RLL = (0x80 << TMR2RLL_TMR2RLL__SHIFT);
	// [TMR2RLL - Timer 2 Reload Low Byte]$

	// $[TMR2CN0]
	/*
	 // Start Timer 2 running
	 */
	TMR2CN0 |= TMR2CN0_TR2__RUN;
	// [TMR2CN0]$

	// $[Timer Restoration]
	// Restore Timer Configuration
	TMR2CN0 |= TMR2CN0_TR2_save;
	// [Timer Restoration]$

}

//================================================================================
// TIMER16_3_enter_DefaultMode_from_RESET
//================================================================================
extern void TIMER16_3_enter_DefaultMode_from_RESET(void) {
	// $[Timer Initialization]
	// Save Timer Configuration
	uint8_t TMR3CN0_TR3_save;
	TMR3CN0_TR3_save = TMR3CN0 & TMR3CN0_TR3__BMASK;
	// Stop Timer
	TMR3CN0 &= ~(TMR3CN0_TR3__BMASK);
	// [Timer Initialization]$

	// $[TMR3CN1 - Timer 3 Control 1]
	// [TMR3CN1 - Timer 3 Control 1]$

	// $[TMR3CN0 - Timer 3 Control]
	// [TMR3CN0 - Timer 3 Control]$

	// $[TMR3H - Timer 3 High Byte]
	// [TMR3H - Timer 3 High Byte]$

	// $[TMR3L - Timer 3 Low Byte]
	// [TMR3L - Timer 3 Low Byte]$

	// $[TMR3RLH - Timer 3 Reload High Byte]
	// [TMR3RLH - Timer 3 Reload High Byte]$

	// $[TMR3RLL - Timer 3 Reload Low Byte]
	// [TMR3RLL - Timer 3 Reload Low Byte]$

	// $[TMR3CN0]
	/*
	 // Start Timer 3 running
	 */
	TMR3CN0 |= TMR3CN0_TR3__RUN;
	// [TMR3CN0]$

	// $[Timer Restoration]
	// Restore Timer Configuration
	TMR3CN0 |= TMR3CN0_TR3_save;
	// [Timer Restoration]$

}

//================================================================================
// TIMER_SETUP_0_enter_DefaultMode_from_RESET
//================================================================================
extern void TIMER_SETUP_0_enter_DefaultMode_from_RESET(void) {
	// $[CKCON0 - Clock Control 0]
	/*
	 // System clock divided by 12
	 // Counter/Timer 0 uses the system clock
	 // Timer 2 high byte uses the clock defined by T2XCLK in TMR2CN0
	 // Timer 2 low byte uses the system clock
	 // Timer 3 high byte uses the clock defined by T3XCLK in TMR3CN0
	 // Timer 3 low byte uses the clock defined by T3XCLK in TMR3CN0
	 // Timer 1 uses the system clock
	 */
	CKCON0 = CKCON0_SCA__SYSCLK_DIV_12 | CKCON0_T0M__SYSCLK
			| CKCON0_T2MH__EXTERNAL_CLOCK | CKCON0_T2ML__SYSCLK
			| CKCON0_T3MH__EXTERNAL_CLOCK | CKCON0_T3ML__EXTERNAL_CLOCK
			| CKCON0_T1M__SYSCLK;
	// [CKCON0 - Clock Control 0]$

	// $[CKCON1 - Clock Control 1]
	// [CKCON1 - Clock Control 1]$

	// $[TMOD - Timer 0/1 Mode]
	/*
	 // Mode 1, 16-bit Counter/Timer
	 // Mode 2, 8-bit Counter/Timer with Auto-Reload
	 // Timer Mode. Timer 0 increments on the clock defined by T0M in the
	 //     CKCON0 register
	 // Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level
	 // Timer Mode. Timer 1 increments on the clock defined by T1M in the
	 //     CKCON0 register
	 // Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level
	 */
	TMOD = TMOD_T0M__MODE1 | TMOD_T1M__MODE2 | TMOD_CT0__TIMER
			| TMOD_GATE0__DISABLED | TMOD_CT1__TIMER | TMOD_GATE1__DISABLED;
	// [TMOD - Timer 0/1 Mode]$

	// $[TCON - Timer 0/1 Control]
	/*
	 // Start Timer 1 running
	 */
	TCON |= TCON_TR1__RUN;
	// [TCON - Timer 0/1 Control]$

}

//================================================================================
// SMBUS_0_enter_DefaultMode_from_RESET
//================================================================================
extern void SMBUS_0_enter_DefaultMode_from_RESET(void) {
	// $[SMB0ADR - SMBus 0 Slave Address]
	// [SMB0ADR - SMBus 0 Slave Address]$

	// $[SMB0ADM - SMBus 0 Slave Address Mask]
	// [SMB0ADM - SMBus 0 Slave Address Mask]$

	// $[SMB0TC - SMBus 0 Timing and Pin Control]
	// [SMB0TC - SMBus 0 Timing and Pin Control]$

	// $[SMB0CF - SMBus 0 Configuration]
	/*
	 // Timer 2 Low Byte Overflow
	 // Enable the SMBus module
	 // Enable bus free timeouts. The bus the bus will be considered free if
	 //     SCL and SDA remain high for more than 10 SMBus clock source periods
	 // Enable SCL low timeouts
	 // Enable SDA extended setup and hold times
	 */
	SMB0CF |= SMB0CF_SMBCS__TIMER2_LOW | SMB0CF_ENSMB__ENABLED
			| SMB0CF_SMBFTE__FREE_TO_ENABLED | SMB0CF_SMBTOE__SCL_TO_ENABLED
			| SMB0CF_EXTHOLD__ENABLED;
	// [SMB0CF - SMBus 0 Configuration]$

	// $[SMB0FCN0 - SMBus0 FIFO Control 0]
	// [SMB0FCN0 - SMBus0 FIFO Control 0]$

	// $[SMB0RXLN - SMBus0 Receive Length Counter]
	// [SMB0RXLN - SMBus0 Receive Length Counter]$

}

//================================================================================
// UART_0_enter_DefaultMode_from_RESET
//================================================================================
extern void UART_0_enter_DefaultMode_from_RESET(void) {
	// $[SCON0 - UART0 Serial Port Control]
	/*
	 // UART0 reception enabled
	 */
	SCON0 |= SCON0_REN__RECEIVE_ENABLED;
	// [SCON0 - UART0 Serial Port Control]$

}

//================================================================================
// INTERRUPT_0_enter_DefaultMode_from_RESET
//================================================================================
extern void INTERRUPT_0_enter_DefaultMode_from_RESET(void) {
	// $[EIE1 - Extended Interrupt Enable 1]
	/*
	 // Disable ADC0 Conversion Complete interrupt
	 // Disable ADC0 Window Comparison interrupt
	 // Disable CP0 interrupts
	 // Disable CP1 interrupts
	 // Disable all Port Match interrupts
	 // Disable all PCA0 interrupts
	 // Enable interrupt requests generated by SMB0
	 // Enable interrupt requests generated by the TF3L or TF3H flags
	 */
	EIE1 = EIE1_EADC0__DISABLED | EIE1_EWADC0__DISABLED | EIE1_ECP0__DISABLED
			| EIE1_ECP1__DISABLED | EIE1_EMAT__DISABLED | EIE1_EPCA0__DISABLED
			| EIE1_ESMB0__ENABLED | EIE1_ET3__ENABLED;
	// [EIE1 - Extended Interrupt Enable 1]$

	// $[EIE2 - Extended Interrupt Enable 2]
	// [EIE2 - Extended Interrupt Enable 2]$

	// $[EIP1H - Extended Interrupt Priority 1 High]
	// [EIP1H - Extended Interrupt Priority 1 High]$

	// $[EIP1 - Extended Interrupt Priority 1 Low]
	// [EIP1 - Extended Interrupt Priority 1 Low]$

	// $[EIP2 - Extended Interrupt Priority 2]
	// [EIP2 - Extended Interrupt Priority 2]$

	// $[EIP2H - Extended Interrupt Priority 2 High]
	// [EIP2H - Extended Interrupt Priority 2 High]$

	// $[IE - Interrupt Enable]
	/*
	 // Enable each interrupt according to its individual mask setting
	 // Disable external interrupt 0
	 // Disable external interrupt 1
	 // Disable all SPI0 interrupts
	 // Disable all Timer 0 interrupt
	 // Disable all Timer 1 interrupt
	 // Enable interrupt requests generated by the TF2L or TF2H flags
	 // Disable UART0 interrupt
	 */
	IE = IE_EA__ENABLED | IE_EX0__DISABLED | IE_EX1__DISABLED
			| IE_ESPI0__DISABLED | IE_ET0__DISABLED | IE_ET1__DISABLED
			| IE_ET2__ENABLED | IE_ES0__DISABLED;
	// [IE - Interrupt Enable]$

	// $[IP - Interrupt Priority]
	// [IP - Interrupt Priority]$

	// $[IPH - Interrupt Priority High]
	// [IPH - Interrupt Priority High]$

}

//================================================================================
// USBLIB_0_enter_DefaultMode_from_RESET
//================================================================================
extern void USBLIB_0_enter_DefaultMode_from_RESET(void) {
	// $[USBD Init]
	USBD_Init (&initstruct);
	// [USBD Init]$

}

extern void PCA_0_enter_DefaultMode_from_RESET(void) {

	// $[PCA Off]
	PCA0CN0_CR = PCA0CN0_CR__STOP;
	// [PCA Off]$

	// $[PCA0MD - PCA Mode]
	// [PCA0MD - PCA Mode]$

	// $[PCA0CENT - PCA Center Alignment Enable]
	// [PCA0CENT - PCA Center Alignment Enable]$

	// $[PCA0CLR - PCA Comparator Clear Control]
	// [PCA0CLR - PCA Comparator Clear Control]$

	// $[PCA0L - PCA Counter/Timer Low Byte]
	// [PCA0L - PCA Counter/Timer Low Byte]$

	// $[PCA0H - PCA Counter/Timer High Byte]
	// [PCA0H - PCA Counter/Timer High Byte]$

	// $[PCA0POL - PCA Output Polarity]
	// [PCA0POL - PCA Output Polarity]$

	// $[PCA0PWM - PCA PWM Configuration]
	// [PCA0PWM - PCA PWM Configuration]$

	// $[PCA On]
	PCA0CN0_CR = PCA0CN0_CR__RUN;
	// [PCA On]$

}

extern void PCACH_0_enter_DefaultMode_from_RESET(void) {

	// $[PCA0 Settings Save]
	// Select Capture/Compare register)
	PCA0PWM &= ~PCA0PWM_ARSEL__BMASK;
	// [PCA0 Settings Save]$

	// $[PCA0CPM0 - PCA Channel 0 Capture/Compare Mode]
	/*
	 // Disable negative edge capture
	 // Disable CCF0 interrupts
	 // Disable match function
	 // 8 to 11-bit PWM selected
	 // Disable positive edge capture
	 // Enable comparator function
	 // Enable PWM function
	 // Disable toggle function
	 */
	PCA0CPM0 = PCA0CPM0_CAPN__DISABLED | PCA0CPM0_ECCF__DISABLED
			| PCA0CPM0_MAT__DISABLED | PCA0CPM0_PWM16__8_BIT
			| PCA0CPM0_CAPP__DISABLED | PCA0CPM0_ECOM__ENABLED
			| PCA0CPM0_PWM__ENABLED | PCA0CPM0_TOG__DISABLED;
	// [PCA0CPM0 - PCA Channel 0 Capture/Compare Mode]$

	// $[PCA0CPL0 - PCA Channel 0 Capture Module Low Byte]
	/*
	 // PCA Channel 0 Capture Module Low Byte = 0x96
	 */
	PCA0CPL0 = (0x96 << PCA0CPL0_PCA0CPL0__SHIFT);
	// [PCA0CPL0 - PCA Channel 0 Capture Module Low Byte]$

	// $[PCA0CPH0 - PCA Channel 0 Capture Module High Byte]
	/*
	 // PCA Channel 0 Capture Module High Byte = 0x96
	 */
	PCA0CPH0 = (0x96 << PCA0CPH0_PCA0CPH0__SHIFT);
	// [PCA0CPH0 - PCA Channel 0 Capture Module High Byte]$

	// $[Auto-reload]
	// [Auto-reload]$

	// $[PCA0 Settings Restore]
	// [PCA0 Settings Restore]$

}

extern void PCACH_1_enter_DefaultMode_from_RESET(void) {

	// $[PCA0 Settings Save]
	// Select Capture/Compare register)
	PCA0PWM &= ~PCA0PWM_ARSEL__BMASK;
	// [PCA0 Settings Save]$

	// $[PCA0CPM1 - PCA Channel 1 Capture/Compare Mode]
	/*
	 // Disable negative edge capture
	 // Disable CCF1 interrupts
	 // Disable match function
	 // 8 to 11-bit PWM selected
	 // Disable positive edge capture
	 // Enable comparator function
	 // Enable PWM function
	 // Disable toggle function
	 */
	PCA0CPM1 = PCA0CPM1_CAPN__DISABLED | PCA0CPM1_ECCF__DISABLED
			| PCA0CPM1_MAT__DISABLED | PCA0CPM1_PWM16__8_BIT
			| PCA0CPM1_CAPP__DISABLED | PCA0CPM1_ECOM__ENABLED
			| PCA0CPM1_PWM__ENABLED | PCA0CPM1_TOG__DISABLED;
	// [PCA0CPM1 - PCA Channel 1 Capture/Compare Mode]$

	// $[PCA0CPL1 - PCA Channel 1 Capture Module Low Byte]
	/*
	 // PCA Channel 1 Capture Module Low Byte = 0x96
	 */
	PCA0CPL1 = (0x96 << PCA0CPL1_PCA0CPL1__SHIFT);
	// [PCA0CPL1 - PCA Channel 1 Capture Module Low Byte]$

	// $[PCA0CPH1 - PCA Channel 1 Capture Module High Byte]
	/*
	 // PCA Channel 1 Capture Module High Byte = 0x96
	 */
	PCA0CPH1 = (0x96 << PCA0CPH1_PCA0CPH1__SHIFT);
	// [PCA0CPH1 - PCA Channel 1 Capture Module High Byte]$

	// $[Auto-reload]
	// [Auto-reload]$

	// $[PCA0 Settings Restore]
	// [PCA0 Settings Restore]$

}

extern void PCACH_2_enter_DefaultMode_from_RESET(void) {

	// $[PCA0 Settings Save]
	// Select Capture/Compare register)
	PCA0PWM &= ~PCA0PWM_ARSEL__BMASK;
	// [PCA0 Settings Save]$

	// $[PCA0CPM2 - PCA Channel 2 Capture/Compare Mode]
	/*
	 // Disable negative edge capture
	 // Disable CCF2 interrupts
	 // Disable match function
	 // 8 to 11-bit PWM selected
	 // Disable positive edge capture
	 // Enable comparator function
	 // Enable PWM function
	 // Disable toggle function
	 */
	PCA0CPM2 = PCA0CPM2_CAPN__DISABLED | PCA0CPM2_ECCF__DISABLED
			| PCA0CPM2_MAT__DISABLED | PCA0CPM2_PWM16__8_BIT
			| PCA0CPM2_CAPP__DISABLED | PCA0CPM2_ECOM__ENABLED
			| PCA0CPM2_PWM__ENABLED | PCA0CPM2_TOG__DISABLED;
	// [PCA0CPM2 - PCA Channel 2 Capture/Compare Mode]$

	// $[PCA0CPL2 - PCA Channel 2 Capture Module Low Byte]
	/*
	 // PCA Channel 2 Capture Module Low Byte = 0x96
	 */
	PCA0CPL2 = (0x96 << PCA0CPL2_PCA0CPL2__SHIFT);
	// [PCA0CPL2 - PCA Channel 2 Capture Module Low Byte]$

	// $[PCA0CPH2 - PCA Channel 2 Capture Module High Byte]
	/*
	 // PCA Channel 2 Capture Module High Byte = 0x96
	 */
	PCA0CPH2 = (0x96 << PCA0CPH2_PCA0CPH2__SHIFT);
	// [PCA0CPH2 - PCA Channel 2 Capture Module High Byte]$

	// $[Auto-reload]
	// [Auto-reload]$

	// $[PCA0 Settings Restore]
	// [PCA0 Settings Restore]$

}