kopia lustrzana https://github.com/stlink-org/stlink
86 wiersze
1.8 KiB
ArmAsm
86 wiersze
1.8 KiB
ArmAsm
.syntax unified
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.text
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/*
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* Arguments:
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* r0 - source memory ptr
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* r1 - target memory ptr
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* r2 - count of bytes
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* r3 - flash register offset
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*/
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.global copy
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copy:
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/*
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* These two NOPs here are a safety precaution, added by Pekka Nikander
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* while debugging the STM32F05x support. They may not be needed, but
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* there were strange problems with simpler programs, like a program
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* that had just a breakpoint or a program that first moved zero to register r2
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* and then had a breakpoint. So, it appears safest to have these two nops.
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*
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* Feel free to remove them, if you dare, but then please do test the result
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* rigorously. Also, if you remove these, it may be a good idea first to
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* #if 0 them out, with a comment when these were taken out, and to remove
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* these only a few months later... But YMMV.
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*/
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nop
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nop
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# load flash control register address
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# add r3 to flash_base for support dual bank (see flash_loader.c)
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ldr r7, flash_base
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add r7, r7, r3
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ldr r6, flash_off_cr
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add r6, r6, r7
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ldr r5, flash_off_sr
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add r5, r5, r7
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# FLASH_CR = 0x01 (set PG)
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ldr r4, =0x1
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str r4, [r6]
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loop:
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# copy 2 bytes
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ldrh r4, [r0]
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strh r4, [r1]
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# increment address
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adds r0, r0, #0x2
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adds r1, r1, #0x2
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# BUSY flag
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ldr r7, =0x01
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wait:
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# get FLASH_SR
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ldr r4, [r5]
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# wait until BUSY flag is reset
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tst r4, r7
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bne wait
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# test PGERR or WRPRTERR flag is reset
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ldr r7, =0x14
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tst r4, r7
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bne exit
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# loop if count > 0
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subs r2, r2, #0x2
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bgt loop
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exit:
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# FLASH_CR &= ~1
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ldr r7, =0x1
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ldr r4, [r6]
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bics r4, r4, r7
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str r4, [r6]
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bkpt
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.align 2
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flash_base:
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.word 0x40022000
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flash_off_cr:
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.word 0x10
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flash_off_sr:
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.word 0x0c
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