Guillaume Revaillot
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6f0795d931
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chipid: add some l0 and l4 option info to allow option byte read
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2020-04-16 15:57:39 +02:00 |
Guillaume Revaillot
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8430a6e6fa
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add read, write option byte for g4 and g0
use g0 code, same logic with different base address.
also cleanup some duplicate lock/unlock code.
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2020-04-16 15:57:39 +02:00 |
nightwalker-87
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b40c2436b6
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Hotfix: Reverts commit 6692fdc .
CKS32-Clone-Patch broke flashing on STM32 F3xx, F4xx and L1xx. (#761)
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2020-03-16 11:36:21 +01:00 |
nightwalker-87
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751da606ca
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Merge branch 'pr-847/zx81a/master' into develop.
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2020-02-21 01:07:52 +01:00 |
nightwalker-87
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6692fdc57c
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Restored support for STM32-Clones
-> CKS devices with Core ID 0x2ba01477
(Closes #756 #757 #761 #766 #769 #805)
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2020-02-21 00:50:50 +01:00 |
orie
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4eec4d8cb9
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Add Option Byte Write command for STM32F2 series.
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2019-10-07 14:46:36 +09:00 |
Adrian Imboden
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e56de83ec5
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added support for writing option bytes on STM32L0
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2019-09-06 18:23:37 +02:00 |
Manuel Dipolt
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c6836b4ac9
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Added support to write option bytes for the STM32G0 (#778)
* poc worked, writting stm32G070 option bytes
* Update README.md
adjust layout
* code review changes
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2019-03-20 14:01:11 +01:00 |