kopia lustrzana https://github.com/stlink-org/stlink
Move all the flash size mapping from gdb server into core.
All the device params like flash size and page size should all be in the core open routines, not _only_ in the gdbserver. (This should stop it from ending up duplicated in the core, and get rid of some of the hacks that were turning up. All of this is chip specific!)pull/29/head
Karl Palsson
rodzic
6cc3375151
commit
5a5d36fdc3
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@ -45,39 +45,6 @@ static const char* current_memory_map = NULL;
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#define CORE_M3_R2 0x4BA00477
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#define CORE_M4_R0 0x2BA01477
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struct chip_params {
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uint32_t chip_id;
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char* description;
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uint32_t flash_size_reg;
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uint32_t max_flash_size, flash_pagesize;
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uint32_t sram_size;
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uint32_t bootrom_base, bootrom_size;
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} const devices[] = {
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{ 0x410, "F1 Medium-density device", 0x1ffff7e0,
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0x20000, 0x400, 0x5000, 0x1ffff000, 0x800 }, // table 2, pm0063
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{ 0x411, "F2 device", 0, /* No flash size register found in the docs*/
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0x100000, 0x20000, 0x20000, 0x1fff0000, 0x7800 }, // table 1, pm0059
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{ 0x412, "F1 Low-density device", 0x1ffff7e0,
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0x8000, 0x400, 0x2800, 0x1ffff000, 0x800 }, // table 1, pm0063
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{ 0x413, "F4 device", 0x1FFF7A10,
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0x100000, 0x20000, 0x30000, 0x1fff0000, 0x7800 }, // table 1, pm0081
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{ 0x414, "F1 High-density device", 0x1ffff7e0,
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0x80000, 0x800, 0x10000, 0x1ffff000, 0x800 }, // table 3 pm0063
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// This ignores the EEPROM! (and uses the page erase size,
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// not the sector write protection...)
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{ 0x416, "L1 Med-density device", 0x1FF8004C, // table 1, pm0062
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0x20000, 0x100, 0x4000, 0x1ff00000, 0x1000 },
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{ 0x418, "F1 Connectivity line device", 0x1ffff7e0,
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0x40000, 0x800, 0x10000, 0x1fffb000, 0x4800 },
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{ 0x420, "F1 Medium-density value line device", 0x1ffff7e0,
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0x20000, 0x400, 0x2000, 0x1ffff000, 0x800 },
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{ 0x428, "F1 High-density value line device", 0x1ffff7e0,
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0x80000, 0x800, 0x8000, 0x1ffff000, 0x800 },
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{ 0x430, "F1 XL-density device", 0x1ffff7e0, // pm0068
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0x100000, 0x800, 0x18000, 0x1fffe000, 0x1800 },
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{ 0 }
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};
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typedef struct _st_state_t {
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// things from command line, bleh
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int stlink_version;
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@ -89,7 +56,7 @@ typedef struct _st_state_t {
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int serve(stlink_t *sl, int port);
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char* make_memory_map(const struct chip_params *params, uint32_t flash_size);
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char* make_memory_map(stlink_t *sl);
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int parse_options(int argc, char** argv, st_state_t *st) {
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@ -201,6 +168,8 @@ int main(int argc, char** argv) {
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if(sl == NULL) return 1;
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break;
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}
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// ALLLL of this should move into "stlink_open_xxx"
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if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) {
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if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) {
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@ -220,34 +189,7 @@ int main(int argc, char** argv) {
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printf("Chip ID is %08x, Core ID is %08x.\n", chip_id, core_id);
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const struct chip_params* params = NULL;
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for(int i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
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if(devices[i].chip_id == (chip_id & 0xFFF)) {
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params = &devices[i];
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break;
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}
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}
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if(params == NULL) {
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fprintf(stderr, "Cannot recognize the connected device!\n");
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return 0;
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}
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printf("Device connected: %s\n", params->description);
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printf("Device parameters: SRAM: 0x%x bytes, Flash: up to 0x%x bytes in pages of 0x%x bytes\n",
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params->sram_size, params->max_flash_size, params->flash_pagesize);
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FLASH_PAGE = params->flash_pagesize;
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uint32_t flash_size;
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stlink_read_mem32(sl, params->flash_size_reg, 4);
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flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8);
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printf("Flash size is %d KiB.\n", flash_size);
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// memory map is in 1k blocks.
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current_memory_map = make_memory_map(params, flash_size * 0x400);
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current_memory_map = make_memory_map(sl);
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while(serve(sl, state.listen_port) == 0);
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@ -275,16 +217,16 @@ static const char* const memory_map_template =
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" <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x8\"/>" // option byte area
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"</memory-map>";
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char* make_memory_map(const struct chip_params *params, uint32_t flash_size) {
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char* make_memory_map(stlink_t *sl) {
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/* This will be freed in serve() */
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char* map = malloc(4096);
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map[0] = '\0';
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snprintf(map, 4096, memory_map_template,
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flash_size,
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params->sram_size,
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flash_size, params->flash_pagesize,
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params->bootrom_base, params->bootrom_size);
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sl->flash_size,
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sl->sram_size,
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sl->flash_size, sl->flash_pgsz,
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sl->sys_base, sl->sys_size);
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return map;
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}
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@ -305,6 +305,50 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
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return;
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}
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/**
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* reads and decodes the flash parameters, as dynamically as possible
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* @param sl
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* @return 0 for success, or -1 for unsupported core type.
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*/
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int stlink_load_device_params(stlink_t *sl) {
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ILOG("Loading device parameters....\n");
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chip_params_t *params = NULL;
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uint32_t chip_id = stlink_chip_id(sl);
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for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
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if(devices[i].chip_id == (chip_id & 0xFFF)) {
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params = &devices[i];
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break;
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}
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}
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if (params == NULL) {
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WLOG("unknown chip id! %#x\n", chip_id);
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return -1;
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}
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// These are fixed...
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sl->flash_base = STM32_FLASH_BASE;
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sl->sram_base = STM32_SRAM_BASE;
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// read flash size from hardware, if possible...
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if ((chip_id & 0xFFF) == STM32_CHIPID_F2) {
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sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible?
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} else {
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stlink_read_mem32(sl, params->flash_size_reg, 4);
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uint32_t flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8);
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sl->flash_size = flash_size * 1024;
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}
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sl->flash_pgsz = params->flash_pagesize;
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sl->sram_size = params->sram_size;
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sl->sys_base = params->bootrom_base;
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sl->sys_size = params->bootrom_size;
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ILOG("Device connected is: %s\n", params->description);
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ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
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sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
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sl->flash_pgsz);
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return 0;
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}
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void stlink_reset(stlink_t *sl) {
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DLOG("*** stlink_reset ***\n");
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sl->backend->reset(sl);
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@ -80,10 +80,134 @@ extern "C" {
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#define STM32VL_CORE_ID 0x1ba01477
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#define STM32L_CORE_ID 0x2ba01477
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#define STM32F4_CORE_ID 0x2ba01477
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// stm32 chipids, only lower 12 bits..
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#define STM32_CHIPID_F1_MEDIUM 0x410
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#define STM32_CHIPID_F2 0x411
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#define STM32_CHIPID_F1_LOW 0x412
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#define STM32_CHIPID_F4 0x413
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#define STM32_CHIPID_F1_HIGH 0x414
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#define STM32_CHIPID_L1_MEDIUM 0x416
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#define STM32_CHIPID_F1_CONN 0x418
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#define STM32_CHIPID_F1_VL_MEDIUM 0x420
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#define STM32_CHIPID_F1_VL_HIGH 0x428
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#define STM32_CHIPID_F1_XL 0x430
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// Constant STM32 memory map figures
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#define STM32_FLASH_BASE 0x08000000
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#define STM32_SRAM_BASE 0x20000000
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/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
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#define C_BUF_LEN 32
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typedef struct chip_params_ {
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uint32_t chip_id;
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char* description;
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uint32_t flash_size_reg;
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uint32_t flash_pagesize;
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uint32_t sram_size;
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uint32_t bootrom_base, bootrom_size;
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} chip_params_t;
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// These maps are from a combination of the Programming Manuals, and
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// also the Reference manuals. (flash size reg is normally in ref man)
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static const chip_params_t devices[] = {
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{ // table 2, PM0063
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.chip_id = 0x410,
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.description = "F1 Medium-density device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x400,
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.sram_size = 0x5000,
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.bootrom_base = 0x1ffff000,
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.bootrom_size = 0x800
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},
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{ // table 1, PM0059
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.chip_id = 0x411,
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.description = "F2 device",
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.flash_size_reg = 0, /* no flash size reg found in the docs! */
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.flash_pagesize = 0x20000,
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.sram_size = 0x20000,
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.bootrom_base = 0x1fff0000,
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.bootrom_size = 0x7800
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},
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{ // PM0063
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.chip_id = 0x412,
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.description = "F1 Low-density device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x400,
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.sram_size = 0x2800,
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.bootrom_base = 0x1ffff000,
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.bootrom_size = 0x800
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},
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{
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.chip_id = 0x413,
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.description = "F4 device",
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.flash_size_reg = 0x1FFF7A10,
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.flash_pagesize = 0x20000,
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.sram_size = 0x30000,
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.bootrom_base = 0x1fff0000,
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.bootrom_size = 0x7800
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},
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{
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.chip_id = 0x414,
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.description = "F1 High-density device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x800,
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.sram_size = 0x10000,
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.bootrom_base = 0x1ffff000,
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.bootrom_size = 0x800
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},
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{
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// This ignores the EEPROM! (and uses the page erase size,
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// not the sector write protection...)
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.chip_id = 0x416,
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.description = "L1 Med-density device",
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.flash_size_reg = 0x1ff8004c,
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.flash_pagesize = 0x100,
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.sram_size = 0x4000,
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.bootrom_base = 0x1ff00000,
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.bootrom_size = 0x1000
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},
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{
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.chip_id = 0x418,
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.description = "F1 Connectivity line device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x800,
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.sram_size = 0x10000,
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.bootrom_base = 0x1fffb000,
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.bootrom_size = 0x4800
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},
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{
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.chip_id = 0x420,
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.description = "F1 Medium-density Value Line device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x400,
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.sram_size = 0x2000,
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.bootrom_base = 0x1ffff000,
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.bootrom_size = 0x800
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},
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{
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.chip_id = 0x428,
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.description = "F1 High-density value line device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x800,
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.sram_size = 0x8000,
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.bootrom_base = 0x1ffff000,
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.bootrom_size = 0x800
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},
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{
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.chip_id = 0x430,
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.description = "F1 XL-density device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x800,
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.sram_size = 0x18000,
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.bootrom_base = 0x1fffe000,
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.bootrom_size = 0x1800
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}
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};
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typedef struct {
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uint32_t r[16];
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uint32_t xpsr;
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@ -161,29 +285,21 @@ extern "C" {
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uint32_t core_id;
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int core_stat;
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/* medium density stm32 flash settings */
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#define STM32_FLASH_BASE 0x08000000
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#define STM32_FLASH_SIZE (128 * 1024)
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#define STM32_FLASH_PGSZ 1024
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#define STM32L_FLASH_PGSZ 256
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stm32_addr_t flash_base;
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size_t flash_size;
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size_t flash_pgsz;
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/* in flash system memory */
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#define STM32_SYSTEM_BASE 0x1ffff000
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#define STM32_SYSTEM_SIZE (2 * 1024)
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stm32_addr_t sys_base;
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size_t sys_size;
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/* sram settings */
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#define STM32_SRAM_BASE 0x20000000
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#define STM32_SRAM_SIZE (8 * 1024)
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#define STM32L_SRAM_SIZE (16 * 1024)
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stm32_addr_t sram_base;
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size_t sram_size;
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// bootloader
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stm32_addr_t sys_base;
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size_t sys_size;
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struct stlink_version_ version;
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};
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@ -236,6 +352,7 @@ extern "C" {
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int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
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int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
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int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
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int stlink_load_device_params(stlink_t *sl);
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|
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@ -1100,19 +1100,6 @@ static stlink_t* stlink_open(const int verbose) {
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sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
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slsg->q_addr = 0;
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/* flash memory settings */
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sl->flash_base = STM32_FLASH_BASE;
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sl->flash_size = STM32_FLASH_SIZE;
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sl->flash_pgsz = STM32_FLASH_PGSZ;
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/* system memory */
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sl->sys_base = STM32_SYSTEM_BASE;
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sl->sys_size = STM32_SYSTEM_SIZE;
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/* sram memory settings */
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sl->sram_base = STM32_SRAM_BASE;
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sl->sram_size = STM32_SRAM_SIZE;
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return sl;
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}
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|
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@ -1127,7 +1114,7 @@ stlink_t* stlink_v1_open(const int verbose) {
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}
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stlink_version(sl);
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stlink_load_device_params(sl);
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if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) {
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ugly_log(UERROR, LOG_TAG,
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"WTF? successfully opened, but unable to read version details. BROKEN!\n");
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@ -1160,5 +1147,6 @@ stlink_t* stlink_v1_open(const int verbose) {
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}
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// re-query device info
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stlink_version(sl);
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stlink_load_device_params(sl);
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return sl;
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}
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|
|
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@ -673,45 +673,7 @@ stlink_t* stlink_open_usb(const int verbose) {
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}
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stlink_version(sl);
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/* per device family initialization */
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stlink_core_id(sl);
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if (sl->core_id == STM32L_CORE_ID) {
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/* flash memory settings */
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sl->flash_base = STM32_FLASH_BASE;
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sl->flash_size = STM32_FLASH_SIZE;
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sl->flash_pgsz = STM32L_FLASH_PGSZ;
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/* system memory */
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sl->sys_base = STM32_SYSTEM_BASE;
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sl->sys_size = STM32_SYSTEM_SIZE;
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/* sram memory settings */
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sl->sram_base = STM32_SRAM_BASE;
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sl->sram_size = STM32L_SRAM_SIZE;
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} else if (sl->core_id == STM32VL_CORE_ID) {
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/* flash memory settings */
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sl->flash_base = STM32_FLASH_BASE;
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sl->flash_size = STM32_FLASH_SIZE;
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sl->flash_pgsz = STM32_FLASH_PGSZ;
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/* system memory */
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sl->sys_base = STM32_SYSTEM_BASE;
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sl->sys_size = STM32_SYSTEM_SIZE;
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/* sram memory settings */
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sl->sram_base = STM32_SRAM_BASE;
|
||||
sl->sram_size = STM32_SRAM_SIZE;
|
||||
|
||||
} else {
|
||||
|
||||
fprintf(stderr, "unknown coreid: %x\n", sl->core_id);
|
||||
goto on_libusb_error;
|
||||
|
||||
}
|
||||
stlink_load_device_params(sl);
|
||||
|
||||
error = 0;
|
||||
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue