diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index bcb3c97..ce0549e 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -45,39 +45,6 @@ static const char* current_memory_map = NULL; #define CORE_M3_R2 0x4BA00477 #define CORE_M4_R0 0x2BA01477 -struct chip_params { - uint32_t chip_id; - char* description; - uint32_t flash_size_reg; - uint32_t max_flash_size, flash_pagesize; - uint32_t sram_size; - uint32_t bootrom_base, bootrom_size; -} const devices[] = { - { 0x410, "F1 Medium-density device", 0x1ffff7e0, - 0x20000, 0x400, 0x5000, 0x1ffff000, 0x800 }, // table 2, pm0063 - { 0x411, "F2 device", 0, /* No flash size register found in the docs*/ - 0x100000, 0x20000, 0x20000, 0x1fff0000, 0x7800 }, // table 1, pm0059 - { 0x412, "F1 Low-density device", 0x1ffff7e0, - 0x8000, 0x400, 0x2800, 0x1ffff000, 0x800 }, // table 1, pm0063 - { 0x413, "F4 device", 0x1FFF7A10, - 0x100000, 0x20000, 0x30000, 0x1fff0000, 0x7800 }, // table 1, pm0081 - { 0x414, "F1 High-density device", 0x1ffff7e0, - 0x80000, 0x800, 0x10000, 0x1ffff000, 0x800 }, // table 3 pm0063 - // This ignores the EEPROM! (and uses the page erase size, - // not the sector write protection...) - { 0x416, "L1 Med-density device", 0x1FF8004C, // table 1, pm0062 - 0x20000, 0x100, 0x4000, 0x1ff00000, 0x1000 }, - { 0x418, "F1 Connectivity line device", 0x1ffff7e0, - 0x40000, 0x800, 0x10000, 0x1fffb000, 0x4800 }, - { 0x420, "F1 Medium-density value line device", 0x1ffff7e0, - 0x20000, 0x400, 0x2000, 0x1ffff000, 0x800 }, - { 0x428, "F1 High-density value line device", 0x1ffff7e0, - 0x80000, 0x800, 0x8000, 0x1ffff000, 0x800 }, - { 0x430, "F1 XL-density device", 0x1ffff7e0, // pm0068 - 0x100000, 0x800, 0x18000, 0x1fffe000, 0x1800 }, - { 0 } -}; - typedef struct _st_state_t { // things from command line, bleh int stlink_version; @@ -89,7 +56,7 @@ typedef struct _st_state_t { int serve(stlink_t *sl, int port); -char* make_memory_map(const struct chip_params *params, uint32_t flash_size); +char* make_memory_map(stlink_t *sl); int parse_options(int argc, char** argv, st_state_t *st) { @@ -201,6 +168,8 @@ int main(int argc, char** argv) { if(sl == NULL) return 1; break; } + + // ALLLL of this should move into "stlink_open_xxx" if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { @@ -220,34 +189,7 @@ int main(int argc, char** argv) { printf("Chip ID is %08x, Core ID is %08x.\n", chip_id, core_id); - const struct chip_params* params = NULL; - - for(int i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { - if(devices[i].chip_id == (chip_id & 0xFFF)) { - params = &devices[i]; - break; - } - } - - if(params == NULL) { - fprintf(stderr, "Cannot recognize the connected device!\n"); - return 0; - } - - printf("Device connected: %s\n", params->description); - printf("Device parameters: SRAM: 0x%x bytes, Flash: up to 0x%x bytes in pages of 0x%x bytes\n", - params->sram_size, params->max_flash_size, params->flash_pagesize); - - FLASH_PAGE = params->flash_pagesize; - - uint32_t flash_size; - - stlink_read_mem32(sl, params->flash_size_reg, 4); - flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8); - - printf("Flash size is %d KiB.\n", flash_size); - // memory map is in 1k blocks. - current_memory_map = make_memory_map(params, flash_size * 0x400); + current_memory_map = make_memory_map(sl); while(serve(sl, state.listen_port) == 0); @@ -275,16 +217,16 @@ static const char* const memory_map_template = " " // option byte area ""; -char* make_memory_map(const struct chip_params *params, uint32_t flash_size) { +char* make_memory_map(stlink_t *sl) { /* This will be freed in serve() */ char* map = malloc(4096); map[0] = '\0'; snprintf(map, 4096, memory_map_template, - flash_size, - params->sram_size, - flash_size, params->flash_pagesize, - params->bootrom_base, params->bootrom_size); + sl->flash_size, + sl->sram_size, + sl->flash_size, sl->flash_pgsz, + sl->sys_base, sl->sys_size); return map; } diff --git a/src/stlink-common.c b/src/stlink-common.c index f58c344..89c2630 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -305,6 +305,50 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { return; } +/** + * reads and decodes the flash parameters, as dynamically as possible + * @param sl + * @return 0 for success, or -1 for unsupported core type. + */ +int stlink_load_device_params(stlink_t *sl) { + ILOG("Loading device parameters....\n"); + chip_params_t *params = NULL; + uint32_t chip_id = stlink_chip_id(sl); + for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + if(devices[i].chip_id == (chip_id & 0xFFF)) { + params = &devices[i]; + break; + } + } + if (params == NULL) { + WLOG("unknown chip id! %#x\n", chip_id); + return -1; + } + + // These are fixed... + sl->flash_base = STM32_FLASH_BASE; + sl->sram_base = STM32_SRAM_BASE; + + // read flash size from hardware, if possible... + if ((chip_id & 0xFFF) == STM32_CHIPID_F2) { + sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible? + } else { + stlink_read_mem32(sl, params->flash_size_reg, 4); + uint32_t flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8); + sl->flash_size = flash_size * 1024; + } + sl->flash_pgsz = params->flash_pagesize; + sl->sram_size = params->sram_size; + sl->sys_base = params->bootrom_base; + sl->sys_size = params->bootrom_size; + + ILOG("Device connected is: %s\n", params->description); + ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", + sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, + sl->flash_pgsz); + return 0; +} + void stlink_reset(stlink_t *sl) { DLOG("*** stlink_reset ***\n"); sl->backend->reset(sl); diff --git a/src/stlink-common.h b/src/stlink-common.h index bcd60aa..5534b6f 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -80,10 +80,134 @@ extern "C" { #define STM32VL_CORE_ID 0x1ba01477 #define STM32L_CORE_ID 0x2ba01477 #define STM32F4_CORE_ID 0x2ba01477 + +// stm32 chipids, only lower 12 bits.. +#define STM32_CHIPID_F1_MEDIUM 0x410 +#define STM32_CHIPID_F2 0x411 +#define STM32_CHIPID_F1_LOW 0x412 +#define STM32_CHIPID_F4 0x413 +#define STM32_CHIPID_F1_HIGH 0x414 +#define STM32_CHIPID_L1_MEDIUM 0x416 +#define STM32_CHIPID_F1_CONN 0x418 +#define STM32_CHIPID_F1_VL_MEDIUM 0x420 +#define STM32_CHIPID_F1_VL_HIGH 0x428 +#define STM32_CHIPID_F1_XL 0x430 + +// Constant STM32 memory map figures +#define STM32_FLASH_BASE 0x08000000 +#define STM32_SRAM_BASE 0x20000000 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 + typedef struct chip_params_ { + uint32_t chip_id; + char* description; + uint32_t flash_size_reg; + uint32_t flash_pagesize; + uint32_t sram_size; + uint32_t bootrom_base, bootrom_size; + } chip_params_t; + + + // These maps are from a combination of the Programming Manuals, and + // also the Reference manuals. (flash size reg is normally in ref man) + static const chip_params_t devices[] = { + { // table 2, PM0063 + .chip_id = 0x410, + .description = "F1 Medium-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { // table 1, PM0059 + .chip_id = 0x411, + .description = "F2 device", + .flash_size_reg = 0, /* no flash size reg found in the docs! */ + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { // PM0063 + .chip_id = 0x412, + .description = "F1 Low-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = 0x413, + .description = "F4 device", + .flash_size_reg = 0x1FFF7A10, + .flash_pagesize = 0x20000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = 0x414, + .description = "F1 High-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This ignores the EEPROM! (and uses the page erase size, + // not the sector write protection...) + .chip_id = 0x416, + .description = "L1 Med-density device", + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = 0x418, + .description = "F1 Connectivity line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800 + }, + { + .chip_id = 0x420, + .description = "F1 Medium-density Value Line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = 0x428, + .description = "F1 High-density value line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = 0x430, + .description = "F1 XL-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800 + } + }; + + typedef struct { uint32_t r[16]; uint32_t xpsr; @@ -161,29 +285,21 @@ extern "C" { uint32_t core_id; int core_stat; - - - /* medium density stm32 flash settings */ -#define STM32_FLASH_BASE 0x08000000 -#define STM32_FLASH_SIZE (128 * 1024) #define STM32_FLASH_PGSZ 1024 #define STM32L_FLASH_PGSZ 256 stm32_addr_t flash_base; size_t flash_size; size_t flash_pgsz; - /* in flash system memory */ -#define STM32_SYSTEM_BASE 0x1ffff000 -#define STM32_SYSTEM_SIZE (2 * 1024) - stm32_addr_t sys_base; - size_t sys_size; - /* sram settings */ -#define STM32_SRAM_BASE 0x20000000 #define STM32_SRAM_SIZE (8 * 1024) #define STM32L_SRAM_SIZE (16 * 1024) stm32_addr_t sram_base; size_t sram_size; + + // bootloader + stm32_addr_t sys_base; + size_t sys_size; struct stlink_version_ version; }; @@ -236,6 +352,7 @@ extern "C" { int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size); int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); + int stlink_load_device_params(stlink_t *sl); diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 1868eba..fd10c16 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -1100,19 +1100,6 @@ static stlink_t* stlink_open(const int verbose) { sl->core_stat = STLINK_CORE_STAT_UNKNOWN; slsg->q_addr = 0; - /* flash memory settings */ - sl->flash_base = STM32_FLASH_BASE; - sl->flash_size = STM32_FLASH_SIZE; - sl->flash_pgsz = STM32_FLASH_PGSZ; - - /* system memory */ - sl->sys_base = STM32_SYSTEM_BASE; - sl->sys_size = STM32_SYSTEM_SIZE; - - /* sram memory settings */ - sl->sram_base = STM32_SRAM_BASE; - sl->sram_size = STM32_SRAM_SIZE; - return sl; } @@ -1127,7 +1114,7 @@ stlink_t* stlink_v1_open(const int verbose) { } stlink_version(sl); - + stlink_load_device_params(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { ugly_log(UERROR, LOG_TAG, "WTF? successfully opened, but unable to read version details. BROKEN!\n"); @@ -1160,5 +1147,6 @@ stlink_t* stlink_v1_open(const int verbose) { } // re-query device info stlink_version(sl); + stlink_load_device_params(sl); return sl; } diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 785f7be..b4df70e 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -673,45 +673,7 @@ stlink_t* stlink_open_usb(const int verbose) { } stlink_version(sl); - - /* per device family initialization */ - stlink_core_id(sl); - if (sl->core_id == STM32L_CORE_ID) { - - /* flash memory settings */ - sl->flash_base = STM32_FLASH_BASE; - sl->flash_size = STM32_FLASH_SIZE; - sl->flash_pgsz = STM32L_FLASH_PGSZ; - - /* system memory */ - sl->sys_base = STM32_SYSTEM_BASE; - sl->sys_size = STM32_SYSTEM_SIZE; - - /* sram memory settings */ - sl->sram_base = STM32_SRAM_BASE; - sl->sram_size = STM32L_SRAM_SIZE; - - } else if (sl->core_id == STM32VL_CORE_ID) { - - /* flash memory settings */ - sl->flash_base = STM32_FLASH_BASE; - sl->flash_size = STM32_FLASH_SIZE; - sl->flash_pgsz = STM32_FLASH_PGSZ; - - /* system memory */ - sl->sys_base = STM32_SYSTEM_BASE; - sl->sys_size = STM32_SYSTEM_SIZE; - - /* sram memory settings */ - sl->sram_base = STM32_SRAM_BASE; - sl->sram_size = STM32_SRAM_SIZE; - - } else { - - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); - goto on_libusb_error; - - } + stlink_load_device_params(sl); error = 0;