kopia lustrzana https://github.com/stlink-org/stlink
Add support for STM32L4R9 (#699)
rodzic
d9d17f4cfe
commit
095ef91818
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@ -67,7 +67,8 @@ enum stlink_stm32_chipids {
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STLINK_CHIPID_STM32_F72XXX = 0x452, /* This ID is found on the NucleoF722ZE board */
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STLINK_CHIPID_STM32_F72XXX = 0x452, /* This ID is found on the NucleoF722ZE board */
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STLINK_CHIPID_STM32_L011 = 0x457,
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STLINK_CHIPID_STM32_L011 = 0x457,
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STLINK_CHIPID_STM32_F410 = 0x458,
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STLINK_CHIPID_STM32_F410 = 0x458,
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STLINK_CHIPID_STM32_F413 = 0x463
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STLINK_CHIPID_STM32_F413 = 0x463,
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STLINK_CHIPID_STM32_L4R9 = 0x470 // taken from the STM32L4R9I-DISCO board
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};
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};
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/**
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/**
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14
src/chipid.c
14
src/chipid.c
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@ -432,7 +432,7 @@ static const struct stlink_chipid_params devices[] = {
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.chip_id = STLINK_CHIPID_STM32_L4,
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.chip_id = STLINK_CHIPID_STM32_L4,
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.description = "L4 device",
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.description = "L4 device",
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.flash_type = STLINK_FLASH_TYPE_L4,
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.flash_type = STLINK_FLASH_TYPE_L4,
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.flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671)
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.flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671)
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.flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
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.flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
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// SRAM1 is "up to" 96k in the standard Cortex-M memory map;
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// SRAM1 is "up to" 96k in the standard Cortex-M memory map;
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// SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
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// SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
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@ -441,6 +441,18 @@ static const struct stlink_chipid_params devices[] = {
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.bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
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.bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
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.bootrom_size = 0x7000 // 28k (per bank), same source as base
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.bootrom_size = 0x7000 // 28k (per bank), same source as base
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},
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},
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{
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// STM32L4R9 (maybe others in the L4Rx series too)
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// From DM00310109.pdf
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.chip_id = STLINK_CHIPID_STM32_L4R9,
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.description = "L4R9 device",
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.flash_type = STLINK_FLASH_TYPE_L4,
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.flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049)
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.flash_pagesize = 0x1000, // 4k, section 3.3, pg 97
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.sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000
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.bootrom_base = 0x1fff0000, // 3.3.1, pg 99
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.bootrom_size = 0x7000 // 28k (per bank), same source as base (pg 99)
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},
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{
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{
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// STLINK_CHIPID_STM32_L43X
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// STLINK_CHIPID_STM32_L43X
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// From RM0392.
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// From RM0392.
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@ -306,6 +306,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
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} else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) ||
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} else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) ||
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(sl->chip_id == STLINK_CHIPID_STM32_L43X) ||
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(sl->chip_id == STLINK_CHIPID_STM32_L43X) ||
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(sl->chip_id == STLINK_CHIPID_STM32_L46X) ||
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(sl->chip_id == STLINK_CHIPID_STM32_L46X) ||
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(sl->chip_id == STLINK_CHIPID_STM32_L4R9) ||
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(sl->chip_id == STLINK_CHIPID_STM32_L496X))
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(sl->chip_id == STLINK_CHIPID_STM32_L496X))
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{
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{
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loader_code = loader_code_stm32l4;
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loader_code = loader_code_stm32l4;
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