diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h
index 7cf5b48..bf03703 100644
--- a/include/stlink/chipid.h
+++ b/include/stlink/chipid.h
@@ -67,7 +67,8 @@ enum stlink_stm32_chipids {
 	STLINK_CHIPID_STM32_F72XXX           = 0x452,	/* This ID is found on the NucleoF722ZE board */
 	STLINK_CHIPID_STM32_L011             = 0x457,
 	STLINK_CHIPID_STM32_F410             = 0x458,
-	STLINK_CHIPID_STM32_F413             = 0x463
+	STLINK_CHIPID_STM32_F413             = 0x463,
+	STLINK_CHIPID_STM32_L4R9             = 0x470 // taken from the STM32L4R9I-DISCO board
 };
 
 /**
diff --git a/src/chipid.c b/src/chipid.c
index 7cf8321..705245f 100644
--- a/src/chipid.c
+++ b/src/chipid.c
@@ -432,7 +432,7 @@ static const struct stlink_chipid_params devices[] = {
             .chip_id = STLINK_CHIPID_STM32_L4,
             .description = "L4 device",
             .flash_type = STLINK_FLASH_TYPE_L4,
-            .flash_size_reg = 0x1fff75e0,    // "Flash size data register" (sec 45.2, page 1671)
+            .flash_size_reg = 0x1FFF75e0,    // "Flash size data register" (sec 45.2, page 1671)
             .flash_pagesize = 0x800,         // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
             // SRAM1 is "up to" 96k in the standard Cortex-M memory map;
             // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
@@ -441,6 +441,18 @@ static const struct stlink_chipid_params devices[] = {
             .bootrom_base = 0x1fff0000,      // Tables 4-6, pages 80-81 (Bank 1 system memory)
             .bootrom_size = 0x7000           // 28k (per bank), same source as base
         },
+        {
+            // STM32L4R9 (maybe others in the L4Rx series too)
+            // From DM00310109.pdf
+            .chip_id = STLINK_CHIPID_STM32_L4R9,
+            .description = "L4R9 device",
+            .flash_type = STLINK_FLASH_TYPE_L4,
+            .flash_size_reg = 0x1fff75e0,    // "Flash size data register" (sec 52.2, page 2049)
+            .flash_pagesize = 0x1000,        // 4k, section 3.3, pg 97
+            .sram_size = 0xa0000,            // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000
+            .bootrom_base = 0x1fff0000,      // 3.3.1, pg 99
+            .bootrom_size = 0x7000           // 28k (per bank), same source as base (pg 99)
+        },
         {
             // STLINK_CHIPID_STM32_L43X
             // From RM0392.
diff --git a/src/flash_loader.c b/src/flash_loader.c
index a9eafcd..ed96144 100644
--- a/src/flash_loader.c
+++ b/src/flash_loader.c
@@ -306,7 +306,8 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
     } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) ||
               (sl->chip_id == STLINK_CHIPID_STM32_L43X) ||
               (sl->chip_id == STLINK_CHIPID_STM32_L46X) ||
-	       (sl->chip_id == STLINK_CHIPID_STM32_L496X))
+              (sl->chip_id == STLINK_CHIPID_STM32_L4R9) ||
+	            (sl->chip_id == STLINK_CHIPID_STM32_L496X))
       {
         loader_code = loader_code_stm32l4;
         loader_size = sizeof(loader_code_stm32l4);