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genesys: Return errors as exceptions from *write_0x8c()

merge-requests/101/head
Povilas Kanapickas 2019-07-14 23:40:37 +03:00
rodzic 1e5a7bd4d8
commit 9e15623411
7 zmienionych plików z 26 dodań i 32 usunięć
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7
backend/genesys_gl124.cc
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@ -3428,6 +3428,7 @@ gl124_init(Genesys_Device * dev)
static SANE_Status static SANE_Status
gl124_boot (Genesys_Device * dev, SANE_Bool cold) gl124_boot (Genesys_Device * dev, SANE_Bool cold)
{ {
DBG_HELPER(dbg);
SANE_Status status = SANE_STATUS_GOOD; SANE_Status status = SANE_STATUS_GOOD;
uint8_t val; uint8_t val;
@ -3467,9 +3468,9 @@ gl124_boot (Genesys_Device * dev, SANE_Bool cold)
RIE (sanei_genesys_write_register (dev, REG0B, val)); RIE (sanei_genesys_write_register (dev, REG0B, val));
dev->reg.remove_reg(0x0b); dev->reg.remove_reg(0x0b);
/* set up end access */ //set up end access
RIE (sanei_genesys_write_0x8c (dev, 0x10, 0x0b)); sanei_genesys_write_0x8c(dev, 0x10, 0x0b);
RIE (sanei_genesys_write_0x8c (dev, 0x13, 0x0e)); sanei_genesys_write_0x8c(dev, 0x13, 0x0e);
/* CIS_LINE */ /* CIS_LINE */
SETREG (0x08, REG08_CIS_LINE); SETREG (0x08, REG08_CIS_LINE);

2
backend/genesys_gl841.cc
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@ -565,7 +565,7 @@ gl841_init_lide80 (Genesys_Device * dev)
sanei_genesys_read_register (dev, REG6B, &val); sanei_genesys_read_register (dev, REG6B, &val);
sanei_genesys_write_register (dev, REG6B, 0x06); sanei_genesys_write_register (dev, REG6B, 0x06);
sanei_genesys_write_0x8c (dev, 0x10, 0x94); sanei_genesys_write_0x8c(dev, 0x10, 0x94);
sanei_genesys_write_register (dev, 0x09, 0x10); sanei_genesys_write_register (dev, 0x09, 0x10);
/* set up GPIO : no address, so no bulk write, doesn't written directly either ? */ /* set up GPIO : no address, so no bulk write, doesn't written directly either ? */

17
backend/genesys_gl843.cc
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@ -3953,6 +3953,7 @@ gl843_init_gpio (Genesys_Device * dev)
static SANE_Status static SANE_Status
gl843_boot (Genesys_Device * dev, SANE_Bool cold) gl843_boot (Genesys_Device * dev, SANE_Bool cold)
{ {
DBG_HELPER(dbg);
SANE_Status status = SANE_STATUS_GOOD; SANE_Status status = SANE_STATUS_GOOD;
uint8_t val; uint8_t val;
@ -3972,7 +3973,7 @@ gl843_boot (Genesys_Device * dev, SANE_Bool cold)
{ {
val = 0x11; val = 0x11;
} }
RIE (sanei_genesys_write_0x8c (dev, 0x0f, val)); sanei_genesys_write_0x8c(dev, 0x0f, val);
/* test CHKVER */ /* test CHKVER */
RIE (sanei_genesys_read_register (dev, REG40, &val)); RIE (sanei_genesys_read_register (dev, REG40, &val));
@ -4005,16 +4006,14 @@ gl843_boot (Genesys_Device * dev, SANE_Bool cold)
dev->reg.find_reg(0x0b).value = val; dev->reg.find_reg(0x0b).value = val;
if (dev->model->model_id == MODEL_CANON_CANOSCAN_8400F) { if (dev->model->model_id == MODEL_CANON_CANOSCAN_8400F) {
RIE(sanei_genesys_write_0x8c(dev, 0x1e, 0x01)); sanei_genesys_write_0x8c(dev, 0x1e, 0x01);
RIE(sanei_genesys_write_0x8c(dev, 0x10, 0xb4)); sanei_genesys_write_0x8c(dev, 0x10, 0xb4);
RIE(sanei_genesys_write_0x8c(dev, 0x0f, 0x02)); sanei_genesys_write_0x8c(dev, 0x0f, 0x02);
} }
else if (dev->model->model_id == MODEL_CANON_CANOSCAN_8600F) { else if (dev->model->model_id == MODEL_CANON_CANOSCAN_8600F) {
RIE(sanei_genesys_write_0x8c(dev, 0x10, 0xc8)); sanei_genesys_write_0x8c(dev, 0x10, 0xc8);
} } else {
else sanei_genesys_write_0x8c(dev, 0x10, 0xb4);
{
RIE (sanei_genesys_write_0x8c (dev, 0x10, 0xb4));
} }
/* CLKSET */ /* CLKSET */

12
backend/genesys_gl846.cc
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@ -2609,11 +2609,10 @@ gl846_init_memory_layout (Genesys_Device * dev)
static SANE_Status static SANE_Status
gl846_boot (Genesys_Device * dev, SANE_Bool cold) gl846_boot (Genesys_Device * dev, SANE_Bool cold)
{ {
DBG_HELPER(dbg);
SANE_Status status = SANE_STATUS_GOOD; SANE_Status status = SANE_STATUS_GOOD;
uint8_t val; uint8_t val;
DBGSTART;
/* reset ASIC if cold boot */ /* reset ASIC if cold boot */
if(cold) if(cold)
{ {
@ -2629,7 +2628,7 @@ gl846_boot (Genesys_Device * dev, SANE_Bool cold)
{ {
val = 0x11; val = 0x11;
} }
RIE (sanei_genesys_write_0x8c (dev, 0x0f, val)); sanei_genesys_write_0x8c(dev, 0x0f, val);
/* test CHKVER */ /* test CHKVER */
RIE (sanei_genesys_read_register (dev, REG40, &val)); RIE (sanei_genesys_read_register (dev, REG40, &val));
@ -2658,9 +2657,9 @@ gl846_boot (Genesys_Device * dev, SANE_Bool cold)
RIE (sanei_genesys_write_register (dev, 0x08, dev->reg.find_reg(0x08).value)); RIE (sanei_genesys_write_register (dev, 0x08, dev->reg.find_reg(0x08).value));
} }
/* set up clocks */ // set up clocks
RIE (sanei_genesys_write_0x8c (dev, 0x10, 0x0e)); sanei_genesys_write_0x8c(dev, 0x10, 0x0e);
RIE (sanei_genesys_write_0x8c (dev, 0x13, 0x0e)); sanei_genesys_write_0x8c(dev, 0x13, 0x0e);
/* setup gpio */ /* setup gpio */
RIE (gl846_init_gpio (dev)); RIE (gl846_init_gpio (dev));
@ -2671,7 +2670,6 @@ gl846_boot (Genesys_Device * dev, SANE_Bool cold)
SETREG (0xf8, 0x05); SETREG (0xf8, 0x05);
RIE (sanei_genesys_write_register (dev, 0xf8, dev->reg.find_reg(0xf8).value)); RIE (sanei_genesys_write_register (dev, 0xf8, dev->reg.find_reg(0xf8).value));
DBGCOMPLETED;
return SANE_STATUS_GOOD; return SANE_STATUS_GOOD;
} }

10
backend/genesys_gl847.cc
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@ -2724,11 +2724,10 @@ gl847_init_memory_layout (Genesys_Device * dev)
static SANE_Status static SANE_Status
gl847_boot (Genesys_Device * dev, SANE_Bool cold) gl847_boot (Genesys_Device * dev, SANE_Bool cold)
{ {
DBG_HELPER(dgb);
SANE_Status status = SANE_STATUS_GOOD; SANE_Status status = SANE_STATUS_GOOD;
uint8_t val; uint8_t val;
DBGSTART;
/* reset ASIC if cold boot */ /* reset ASIC if cold boot */
if(cold) if(cold)
{ {
@ -2760,9 +2759,9 @@ gl847_boot (Genesys_Device * dev, SANE_Bool cold)
SETREG (0x08, REG08_CIS_LINE); SETREG (0x08, REG08_CIS_LINE);
RIE (sanei_genesys_write_register (dev, 0x08, dev->reg.find_reg(0x08).value)); RIE (sanei_genesys_write_register (dev, 0x08, dev->reg.find_reg(0x08).value));
/* set up end access */ // set up end access
RIE (sanei_genesys_write_0x8c (dev, 0x10, 0x0b)); sanei_genesys_write_0x8c(dev, 0x10, 0x0b);
RIE (sanei_genesys_write_0x8c (dev, 0x13, 0x0e)); sanei_genesys_write_0x8c(dev, 0x13, 0x0e);
/* setup gpio */ /* setup gpio */
RIE (gl847_init_gpio (dev)); RIE (gl847_init_gpio (dev));
@ -2773,7 +2772,6 @@ gl847_boot (Genesys_Device * dev, SANE_Bool cold)
SETREG (0xf8, 0x01); SETREG (0xf8, 0x01);
RIE (sanei_genesys_write_register (dev, 0xf8, dev->reg.find_reg(0xf8).value)); RIE (sanei_genesys_write_register (dev, 0xf8, dev->reg.find_reg(0xf8).value));
DBGCOMPLETED;
return SANE_STATUS_GOOD; return SANE_STATUS_GOOD;
} }

8
backend/genesys_low.cc
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@ -496,13 +496,11 @@ sanei_genesys_write_register (Genesys_Device * dev, uint16_t reg, uint8_t val)
* @param index index of the command * @param index index of the command
* @param val value to write * @param val value to write
*/ */
SANE_Status void sanei_genesys_write_0x8c(Genesys_Device* dev, uint8_t index, uint8_t val)
sanei_genesys_write_0x8c(Genesys_Device * dev, uint8_t index, uint8_t val)
{ {
DBG_HELPER_ARGS(dbg, "0x%02x,0x%02x", index, val); DBG_HELPER_ARGS(dbg, "0x%02x,0x%02x", index, val);
dev->usb_dev.control_msg(REQUEST_TYPE_OUT, REQUEST_REGISTER, VALUE_BUF_ENDACCESS, index, dev->usb_dev.control_msg(REQUEST_TYPE_OUT, REQUEST_REGISTER, VALUE_BUF_ENDACCESS, index, 1,
1, &val); &val);
return SANE_STATUS_GOOD;
} }
/* read reg 0x41: /* read reg 0x41:

2
backend/genesys_low.h
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@ -1730,7 +1730,7 @@ extern SANE_Status
sanei_genesys_bulk_write_register(Genesys_Device * dev, sanei_genesys_bulk_write_register(Genesys_Device * dev,
Genesys_Register_Set& regs); Genesys_Register_Set& regs);
extern SANE_Status sanei_genesys_write_0x8c (Genesys_Device * dev, uint8_t index, uint8_t val); extern void sanei_genesys_write_0x8c(Genesys_Device* dev, uint8_t index, uint8_t val);
extern unsigned sanei_genesys_get_bulk_max_size(Genesys_Device * dev); extern unsigned sanei_genesys_get_bulk_max_size(Genesys_Device * dev);