kopia lustrzana https://github.com/pimoroni/pimoroni-pico
HUB75 Less RAM, DMA flip
Switch from 12-bit to 10-bit gamma to fit RGB into a uint32_t. Simplifies PIO and halves the RAM usage for F/B buffer. Switch "flip" to *literally* swap the front and back buffers, and then asyncronously DMA the new back buffer into the front ready for the next draw.pull/193/head
Phil Howard
rodzic
069ca38ae7
commit
30a455a9d5
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@ -37,7 +37,7 @@ Pixel hsv_to_rgb(float h, float s, float v) {
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}
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Hub75::Hub75(uint8_t width, uint8_t height, Pixel *buffer, PanelType panel_type)
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Hub75::Hub75(uint8_t width, uint8_t height, Pixel *buffer, PanelType panel_type, bool inverted_stb)
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: width(width), height(height), panel_type(panel_type)
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{
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// Set up allllll the GPIO
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@ -167,6 +167,9 @@ void Hub75::start(irq_handler_t handler) {
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hub75_data_rgb888_program_init(pio, sm_data, data_prog_offs, DATA_BASE_PIN, pin_clk);
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hub75_row_program_init(pio, sm_row, row_prog_offs, ROWSEL_BASE_PIN, ROWSEL_N_PINS, pin_stb);
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// Prevent flicker in Python caused by the smaller dataset just blasting through the PIO too quickly
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pio_sm_set_clkdiv(pio, sm_data, 2.0f);
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if(dma_channel_is_claimed(dma_channel)) {
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irq_set_enabled(DMA_IRQ_0, false);
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dma_channel_set_irq0_enabled(dma_channel, false);
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@ -176,6 +179,14 @@ void Hub75::start(irq_handler_t handler) {
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dma_channel_unclaim(dma_channel);
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}
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if(dma_channel_is_claimed(dma_flip_channel)){
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irq_set_enabled(DMA_IRQ_1, false);
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dma_channel_set_irq1_enabled(dma_flip_channel, false);
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irq_remove_handler(DMA_IRQ_1, handler);
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dma_channel_wait_for_finish_blocking(dma_flip_channel);
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dma_channel_unclaim(dma_flip_channel);
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}
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dma_channel_claim(dma_channel);
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dma_channel_config config = dma_channel_get_default_config(dma_channel);
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channel_config_set_transfer_data_size(&config, DMA_SIZE_32);
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@ -184,33 +195,53 @@ void Hub75::start(irq_handler_t handler) {
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dma_channel_configure(dma_channel, &config, &pio->txf[sm_data], NULL, 0, false);
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dma_channel_set_irq0_enabled(dma_channel, true);
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irq_set_enabled(pio_get_dreq(pio, sm_data, true), true);
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dma_channel_claim(dma_flip_channel);
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dma_channel_config flip_config = dma_channel_get_default_config(dma_flip_channel);
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channel_config_set_transfer_data_size(&flip_config, DMA_SIZE_32);
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channel_config_set_read_increment(&flip_config, true);
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channel_config_set_write_increment(&flip_config, true);
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channel_config_set_bswap(&flip_config, false);
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dma_channel_configure(dma_flip_channel, &flip_config, nullptr, nullptr, 0, false);
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dma_channel_set_irq1_enabled(dma_flip_channel, true);
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// Same handler for both DMA channels
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irq_set_exclusive_handler(DMA_IRQ_0, handler);
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irq_set_enabled(DMA_IRQ_0, true);
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irq_set_exclusive_handler(DMA_IRQ_1, handler);
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irq_set_enabled(DMA_IRQ_1, true);
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row = 0;
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bit = 0;
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dma_channel_set_trans_count(dma_channel, width * 4, false);
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dma_channel_set_trans_count(dma_channel, width * 2, false);
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dma_channel_set_read_addr(dma_channel, &back_buffer, true);
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} else {
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while (running) {
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display_update();
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}
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}
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}
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void Hub75::stop(irq_handler_t handler) {
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running = false;
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if(dma_channel_is_claimed(dma_channel)) {
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// stop and release the dma channel
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irq_set_enabled(DMA_IRQ_0, false);
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// stop and release the dma channel
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dma_channel_set_irq0_enabled(dma_channel, false);
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irq_set_enabled(pio_get_dreq(pio, sm_data, true), false);
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irq_remove_handler(DMA_IRQ_0, handler);
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dma_channel_wait_for_finish_blocking(dma_channel);
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dma_channel_unclaim(dma_channel);
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irq_remove_handler(DMA_IRQ_0, handler);
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}
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if(dma_channel_is_claimed(dma_flip_channel)) {
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dma_channel_wait_for_finish_blocking(dma_flip_channel);
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irq_set_enabled(DMA_IRQ_1, false);
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dma_channel_set_irq1_enabled(dma_flip_channel, false);
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dma_channel_unclaim(dma_flip_channel);
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irq_remove_handler(DMA_IRQ_1, handler);
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}
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hub75_wait_tx_stall(pio, sm_row);
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@ -244,60 +275,33 @@ void Hub75::clear() {
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}
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void Hub75::flip() {
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// Flip and block until the front buffer has been prepared
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do_flip = true;
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while(do_flip) {};
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}
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void Hub75::display_update() {
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if (do_flip) {
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memcpy(back_buffer, front_buffer, width * height * sizeof(Pixel));
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do_flip = false;
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}
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for(auto bit = 1u; bit < 1 << 11; bit <<= 1) {
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for(auto y = 0u; y < height / 2; y++) {
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auto row_top = y * width;
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auto row_bottom = (y + height / 2) * width;
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for(auto x = 0u; x < width; x++) {
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Pixel pixel_top = back_buffer[row_top + x];
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Pixel pixel_bottom = back_buffer[row_bottom + x];
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gpio_put(pin_clk, !clk_polarity);
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gpio_put(pin_r0, (bool)(pixel_top.r & bit));
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gpio_put(pin_g0, (bool)(pixel_top.g & bit));
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gpio_put(pin_b0, (bool)(pixel_top.b & bit));
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gpio_put(pin_r1, (bool)(pixel_bottom.r & bit));
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gpio_put(pin_g1, (bool)(pixel_bottom.g & bit));
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gpio_put(pin_b1, (bool)(pixel_bottom.b & bit));
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gpio_put(pin_clk, clk_polarity);
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}
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gpio_put_masked(0b11111 << pin_row_a, y << pin_row_a);
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gpio_put(pin_stb, stb_polarity);
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gpio_put(pin_oe, oe_polarity);
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for(auto s = 0u; s < bit; ++s) {
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asm volatile("nop \nnop");
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}
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gpio_put(pin_stb, !stb_polarity);
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gpio_put(pin_oe, !oe_polarity);
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}
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}
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while(do_flip) {
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best_effort_wfe_or_timeout(make_timeout_time_us(10));
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};
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}
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void Hub75::dma_complete() {
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if (do_flip && bit == 0 && row == 0) {
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memcpy(back_buffer, front_buffer, width * height * sizeof(Pixel));
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if(dma_channel_get_irq1_status(dma_flip_channel)) {
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dma_channel_acknowledge_irq1(dma_flip_channel);
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do_flip = false;
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}
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if(dma_channel_get_irq0_status(dma_channel)) {
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dma_channel_acknowledge_irq0(dma_channel);
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if (do_flip && bit == 0 && row == 0) {
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// Literally flip the front and back buffers by swapping their addresses
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Pixel *tmp = back_buffer;
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back_buffer = front_buffer;
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front_buffer = tmp;
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// Then, read the contents of the back buffer into the front buffer
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dma_channel_set_read_addr(dma_flip_channel, back_buffer, false);
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dma_channel_set_write_addr(dma_flip_channel, front_buffer, false);
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dma_channel_set_trans_count(dma_flip_channel, width * height, true);
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}
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// SM is finished when it stalls on empty TX FIFO (or, y'know, DMA callback)
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hub75_wait_tx_stall(pio, sm_data);
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@ -312,13 +316,13 @@ void Hub75::dma_complete() {
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if(row == height / 2) {
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row = 0;
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bit++;
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if (bit == 12) {
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if (bit == BIT_DEPTH) {
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bit = 0;
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}
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hub75_data_rgb888_set_shift(pio, sm_data, data_prog_offs, bit);
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}
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}
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dma_channel_set_trans_count(dma_channel, width * 4, false); // This count is in uint32_t which is 1/2th the size of Pixel
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dma_channel_set_read_addr(dma_channel, &back_buffer[row * width * 2], true);
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dma_channel_set_trans_count(dma_channel, width * 2, false);
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dma_channel_set_read_addr(dma_channel, &back_buffer[row * width * 2], true);
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}
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}
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@ -11,39 +11,35 @@ const uint DATA_BASE_PIN = 0;
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const uint DATA_N_PINS = 6;
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const uint ROWSEL_BASE_PIN = 6;
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const uint ROWSEL_N_PINS = 5;
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const uint BIT_DEPTH = 10;
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// This gamma table is used to correct our 8-bit (0-255) colours up to 11-bit,
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// allowing us to gamma correct without losing dynamic range.
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constexpr uint16_t GAMMA_12BIT[256] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 50,
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52, 54, 57, 59, 62, 65, 67, 70, 73, 76, 79, 82, 85, 88, 91, 94,
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98, 101, 105, 108, 112, 115, 119, 123, 127, 131, 135, 139, 143, 147, 151, 155,
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160, 164, 169, 173, 178, 183, 187, 192, 197, 202, 207, 212, 217, 223, 228, 233,
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239, 244, 250, 255, 261, 267, 273, 279, 285, 291, 297, 303, 309, 316, 322, 328,
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335, 342, 348, 355, 362, 369, 376, 383, 390, 397, 404, 412, 419, 427, 434, 442,
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449, 457, 465, 473, 481, 489, 497, 505, 513, 522, 530, 539, 547, 556, 565, 573,
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582, 591, 600, 609, 618, 628, 637, 646, 656, 665, 675, 685, 694, 704, 714, 724,
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734, 744, 755, 765, 775, 786, 796, 807, 817, 828, 839, 850, 861, 872, 883, 894,
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905, 917, 928, 940, 951, 963, 975, 987, 998, 1010, 1022, 1035, 1047, 1059, 1071, 1084,
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1096, 1109, 1122, 1135, 1147, 1160, 1173, 1186, 1199, 1213, 1226, 1239, 1253, 1266, 1280, 1294,
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1308, 1321, 1335, 1349, 1364, 1378, 1392, 1406, 1421, 1435, 1450, 1465, 1479, 1494, 1509, 1524,
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1539, 1554, 1570, 1585, 1600, 1616, 1631, 1647, 1663, 1678, 1694, 1710, 1726, 1743, 1759, 1775,
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1791, 1808, 1824, 1841, 1858, 1875, 1891, 1908, 1925, 1943, 1960, 1977, 1994, 2012, 2029, 2047};
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// We don't *need* to make Pixel a fancy struct with RGB values, but it helps.
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#pragma pack(push, 1)
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struct alignas(4) Pixel {
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uint16_t _;
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uint16_t r;
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uint16_t g;
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uint16_t b;
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constexpr Pixel() : _(0), r(0), g(0), b(0) {};
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constexpr Pixel(uint8_t r, uint8_t g, uint8_t b) : _(0), r(GAMMA_12BIT[r]), g(GAMMA_12BIT[g]), b(GAMMA_12BIT[b]) {};
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constexpr uint16_t GAMMA_10BIT[256] = {
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0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8,
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8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16,
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16, 17, 17, 18, 18, 19, 19, 20, 20, 21, 21, 22, 22, 23, 24, 25,
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26, 27, 29, 30, 31, 33, 34, 35, 37, 38, 40, 41, 43, 44, 46, 47,
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49, 51, 53, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78,
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80, 82, 85, 87, 89, 92, 94, 96, 99, 101, 104, 106, 109, 112, 114, 117,
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120, 122, 125, 128, 131, 134, 137, 140, 143, 146, 149, 152, 155, 158, 161, 164,
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168, 171, 174, 178, 181, 185, 188, 192, 195, 199, 202, 206, 210, 214, 217, 221,
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225, 229, 233, 237, 241, 245, 249, 253, 257, 261, 265, 270, 274, 278, 283, 287,
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291, 296, 300, 305, 309, 314, 319, 323, 328, 333, 338, 343, 347, 352, 357, 362,
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367, 372, 378, 383, 388, 393, 398, 404, 409, 414, 420, 425, 431, 436, 442, 447,
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453, 459, 464, 470, 476, 482, 488, 494, 499, 505, 511, 518, 524, 530, 536, 542,
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548, 555, 561, 568, 574, 580, 587, 593, 600, 607, 613, 620, 627, 633, 640, 647,
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654, 661, 668, 675, 682, 689, 696, 703, 711, 718, 725, 733, 740, 747, 755, 762,
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770, 777, 785, 793, 800, 808, 816, 824, 832, 839, 847, 855, 863, 872, 880, 888,
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896, 904, 912, 921, 929, 938, 946, 954, 963, 972, 980, 989, 997, 1006, 1015, 1023
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};
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struct Pixel {
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uint32_t color;
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constexpr Pixel() : color(0) {};
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constexpr Pixel(uint8_t r, uint8_t g, uint8_t b) : color((GAMMA_10BIT[b] << 20) | (GAMMA_10BIT[g] << 10) | GAMMA_10BIT[r]) {};
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};
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#pragma pack(pop)
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enum PanelType {
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PANEL_GENERIC = 0,
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@ -62,6 +58,7 @@ class Hub75 {
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// DMA & PIO
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uint dma_channel = 0;
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uint dma_flip_channel = 1;
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volatile bool do_flip = false;
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uint bit = 0;
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uint row = 0;
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@ -108,8 +105,9 @@ class Hub75 {
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unsigned int pin_led_g = 17;
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unsigned int pin_led_b = 18;
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Hub75(uint8_t width, uint8_t height, Pixel *buffer) : Hub75(width, height, buffer, PANEL_GENERIC) {};
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Hub75(uint8_t width, uint8_t height, Pixel *buffer, PanelType panel_type);
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Hub75(uint8_t width, uint8_t height, Pixel *buffer) : Hub75(width, height, buffer, PANEL_GENERIC, false) {};
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Hub75(uint8_t width, uint8_t height, Pixel *buffer, PanelType panel_type) : Hub75(width, height, buffer, panel_type, false) {};
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Hub75(uint8_t width, uint8_t height, Pixel *buffer, PanelType panel_type, bool inverted_stb);
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~Hub75();
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void FM6126A_write_register(uint16_t value, uint8_t position);
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@ -26,6 +26,28 @@ pulse_loop:
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jmp x-- pulse_loop side 0x0 ; Assert OEn for x+1 cycles
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.wrap
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.program hub75_row_inverted
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; side-set pin 0 is LATCH
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; side-set pin 1 is OEn
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; OUT pins are row select A-E
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;
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; Each FIFO record consists of:
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; - 5-bit row select (LSBs)
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; - Pulse width - 1 (27 MSBs)
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;
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; Repeatedly select a row, pulse LATCH, and generate a pulse of a certain
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; width on OEn.
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.side_set 2
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.wrap_target
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out pins, 5 [7] side 0x3 ; Deassert OEn, output row select
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out x, 27 [7] side 0x2 ; Pulse LATCH, get OEn pulse width
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pulse_loop:
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jmp x-- pulse_loop side 0x1 ; Assert OEn for x+1 cycles
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.wrap
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% c-sdk {
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static inline void hub75_row_program_init(PIO pio, uint sm, uint offset, uint row_base_pin, uint n_row_pins, uint latch_base_pin) {
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pio_sm_set_consecutive_pindirs(pio, sm, row_base_pin, n_row_pins, true);
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@ -74,29 +96,25 @@ public entry_point:
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public shift0: ; R0 G0 B0 (Top half of 64x64 displays)
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pull side 0 ; gets patched to `out null, n` if n nonzero (otherwise the PULL is required for fencing)
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out null, 16 side 0 ; discard _
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in osr, 1 side 0 ; Red0
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out null, 32 side 0 ; discard remaining bits
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in osr, 1 side 0 ; Red0 N
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out null, 10 side 0 ; Red0 discard
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public shift1:
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pull side 0 ; gets patched to out null, n if n is nonzero (otherwise PULL required)
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in osr, 1 side 0 ; Green0
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out null, 16 side 0 ; << next uint16
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in osr, 1 side 0 ; Blue0
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out null, 32 side 0 ; discard remaining bits
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in osr, 1 side 0 ; Green0 N
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out null, 10 side 0 ; Green0 discard
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public shift2:
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pull side 0 ; gets patched to out null, n if n is nonzero (otherwise PULL required)
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out null, 16 side 0 ; discard _
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in osr, 1 side 0 ; Red1
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out null, 32 side 0 ; discard remaining bits
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in osr, 1 side 0 ; Blue0 N
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out null, 32 side 0 ; Remainder discard
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public shift3: ; R1 G1 B1 (Bottom half of 64x64 displays)
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pull side 0 ; gets patched to out null, n if n is nonzero (otherwise PULL required)
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in osr, 1 side 0 ; Green0, CLK rising edge
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out null, 16 side 0 ; << next uint16
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in osr, 1 side 0 ; Blue0
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out null, 32 side 0 ; discard remaining bits
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public shift1: ; R1 G1 B1 (Bottom half of 64x64 displays)
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pull side 0 ; gets patched to `out null, n` if n nonzero (otherwise the PULL is required for fencing)
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in osr, 1 side 0 ; Red1 N
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out null, 10 side 0 ; Red1 discard
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in osr, 1 side 0 ; Green1 N
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out null, 10 side 0 ; Green1 discard
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in osr, 1 side 0 ; Blue1 N
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out null, 32 side 0 ; Remainder discard
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in null, 26 side 0 ; Note we are just doing this little manoeuvre here to get GPIOs in the order
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mov pins, ::isr [7] side 1 ; R0, G0, B0, R1, G1, B1. Can go 1 cycle faster if reversed
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@ -135,7 +153,5 @@ static inline void hub75_data_rgb888_set_shift(PIO pio, uint sm, uint offset, ui
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instr = pio_encode_out(pio_null, shamt);
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pio->instr_mem[offset + hub75_data_rgb888_offset_shift0] = instr;
|
||||
pio->instr_mem[offset + hub75_data_rgb888_offset_shift1] = instr;
|
||||
pio->instr_mem[offset + hub75_data_rgb888_offset_shift2] = instr;
|
||||
pio->instr_mem[offset + hub75_data_rgb888_offset_shift3] = instr;
|
||||
}
|
||||
%}
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue