kopia lustrzana https://github.com/pimoroni/pimoroni-pico
Add support for SD over PIO SPI
Phil Howard
rodzic
bcde0b6784
commit
1e5e4c2f94
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@ -9,4 +9,5 @@ if (NOT TARGET fatfs)
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target_link_libraries(fatfs INTERFACE pico_stdlib hardware_clocks hardware_spi)
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target_include_directories(fatfs INTERFACE ${CMAKE_CURRENT_LIST_DIR})
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endif()
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@ -0,0 +1,84 @@
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/**
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "pio_spi.h"
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// Just 8 bit functions provided here. The PIO program supports any frame size
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// 1...32, but the software to do the necessary FIFO shuffling is left as an
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// exercise for the reader :)
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//
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// Likewise we only provide MSB-first here. To do LSB-first, you need to
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// - Do shifts when reading from the FIFO, for general case n != 8, 16, 32
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// - Do a narrow read at a one halfword or 3 byte offset for n == 16, 8
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// in order to get the read data correctly justified.
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void __time_critical_func(pio_spi_write8_blocking)(const pio_spi_inst_t *spi, const uint8_t *src, size_t len) {
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size_t tx_remain = len, rx_remain = len;
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// Do 8 bit accesses on FIFO, so that write data is byte-replicated. This
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// gets us the left-justification for free (for MSB-first shift-out)
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io_rw_8 *txfifo = (io_rw_8 *) &spi->pio->txf[spi->sm];
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io_rw_8 *rxfifo = (io_rw_8 *) &spi->pio->rxf[spi->sm];
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while (tx_remain || rx_remain) {
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if (tx_remain && !pio_sm_is_tx_fifo_full(spi->pio, spi->sm)) {
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*txfifo = *src++;
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--tx_remain;
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}
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if (rx_remain && !pio_sm_is_rx_fifo_empty(spi->pio, spi->sm)) {
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(void) *rxfifo;
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--rx_remain;
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}
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}
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}
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void __time_critical_func(pio_spi_read8_blocking)(const pio_spi_inst_t *spi, uint8_t *dst, size_t len) {
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size_t tx_remain = len, rx_remain = len;
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io_rw_8 *txfifo = (io_rw_8 *) &spi->pio->txf[spi->sm];
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io_rw_8 *rxfifo = (io_rw_8 *) &spi->pio->rxf[spi->sm];
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while (tx_remain || rx_remain) {
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if (tx_remain && !pio_sm_is_tx_fifo_full(spi->pio, spi->sm)) {
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*txfifo = 0;
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--tx_remain;
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}
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if (rx_remain && !pio_sm_is_rx_fifo_empty(spi->pio, spi->sm)) {
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*dst++ = *rxfifo;
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--rx_remain;
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}
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}
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}
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void __time_critical_func(pio_spi_write8_read8_blocking)(const pio_spi_inst_t *spi, uint8_t *src, uint8_t *dst,
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size_t len) {
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size_t tx_remain = len, rx_remain = len;
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io_rw_8 *txfifo = (io_rw_8 *) &spi->pio->txf[spi->sm];
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io_rw_8 *rxfifo = (io_rw_8 *) &spi->pio->rxf[spi->sm];
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while (tx_remain || rx_remain) {
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if (tx_remain && !pio_sm_is_tx_fifo_full(spi->pio, spi->sm)) {
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*txfifo = *src++;
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--tx_remain;
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}
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if (rx_remain && !pio_sm_is_rx_fifo_empty(spi->pio, spi->sm)) {
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*dst++ = *rxfifo;
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--rx_remain;
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}
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}
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}
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void __time_critical_func(pio_spi_repeat8_read8_blocking)(const pio_spi_inst_t *spi, uint8_t src, uint8_t *dst,
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size_t len) {
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size_t tx_remain = len, rx_remain = len;
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io_rw_8 *txfifo = (io_rw_8 *) &spi->pio->txf[spi->sm];
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io_rw_8 *rxfifo = (io_rw_8 *) &spi->pio->rxf[spi->sm];
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while (tx_remain || rx_remain) {
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if (tx_remain && !pio_sm_is_tx_fifo_full(spi->pio, spi->sm)) {
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*txfifo = src;
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--tx_remain;
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}
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if (rx_remain && !pio_sm_is_rx_fifo_empty(spi->pio, spi->sm)) {
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*dst++ = *rxfifo;
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--rx_remain;
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}
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}
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}
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@ -0,0 +1,26 @@
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/**
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _PIO_SPI_H
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#define _PIO_SPI_H
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#include "hardware/pio.h"
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#include "spi.pio.h"
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typedef struct pio_spi_inst {
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PIO pio;
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uint sm;
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uint cs_pin;
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} pio_spi_inst_t;
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void pio_spi_write8_blocking(const pio_spi_inst_t *spi, const uint8_t *src, size_t len);
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void pio_spi_read8_blocking(const pio_spi_inst_t *spi, uint8_t *dst, size_t len);
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void pio_spi_write8_read8_blocking(const pio_spi_inst_t *spi, uint8_t *src, uint8_t *dst, size_t len);
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void pio_spi_repeat8_read8_blocking(const pio_spi_inst_t *spi, uint8_t src, uint8_t *dst, size_t len);
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#endif
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@ -3,7 +3,11 @@
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#include "pico.h"
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#include "pico/stdlib.h"
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#include "hardware/clocks.h"
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#ifndef SDCARD_PIO
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#include "hardware/spi.h"
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#else
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#include "pio_spi.h"
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#endif
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#include "hardware/gpio.h"
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//#include "hardware/gpio_ex.h"
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@ -55,6 +59,13 @@ DSTATUS Stat = STA_NOINIT; /* Physical drive status */
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static
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BYTE CardType; /* Card type flags */
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#ifdef SDCARD_PIO
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pio_spi_inst_t pio_spi = {
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.pio = SDCARD_PIO,
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.sm = SDCARD_PIO_SM
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};
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#endif
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static inline uint32_t _millis(void)
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{
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return to_ms_since_boot(get_absolute_time());
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@ -78,12 +89,16 @@ static inline void cs_deselect(uint cs_pin) {
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static void FCLK_SLOW(void)
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{
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spi_set_baudrate(spi0, CLK_SLOW);
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#ifndef SDCARD_PIO
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spi_set_baudrate(SDCARD_SPI_BUS, CLK_SLOW);
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#endif
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}
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static void FCLK_FAST(void)
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{
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spi_set_baudrate(spi0, CLK_FAST);
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#ifndef SDCARD_PIO
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spi_set_baudrate(SDCARD_SPI_BUS, CLK_FAST);
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#endif
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}
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static void CS_HIGH(void)
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@ -107,18 +122,15 @@ void init_spi(void)
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//gpio_pull_up(SDCARD_PIN_SPI0_SCK);
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//gpio_set_drive_strength(SDCARD_PIN_SPI0_SCK, PADS_BANK0_GPIO0_DRIVE_VALUE_4MA); // 2mA, 4mA (default), 8mA, 12mA
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//gpio_set_slew_rate(SDCARD_PIN_SPI0_SCK, 0); // 0: SLOW (default), 1: FAST
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gpio_set_function(SDCARD_PIN_SPI0_SCK, GPIO_FUNC_SPI);
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gpio_init(SDCARD_PIN_SPI0_MISO);
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gpio_pull_up(SDCARD_PIN_SPI0_MISO);
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//gpio_set_schmitt(SDCARD_PIN_SPI0_MISO, 1); // 0: Off, 1: On (default)
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gpio_set_function(SDCARD_PIN_SPI0_MISO, GPIO_FUNC_SPI);
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gpio_init(SDCARD_PIN_SPI0_MOSI);
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gpio_pull_up(SDCARD_PIN_SPI0_MOSI);
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//gpio_set_drive_strength(SDCARD_PIN_SPI0_MOSI, PADS_BANK0_GPIO0_DRIVE_VALUE_4MA); // 2mA, 4mA (default), 8mA, 12mA
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//gpio_set_slew_rate(SDCARD_PIN_SPI0_MOSI, 0); // 0: SLOW (default), 1: FAST
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gpio_set_function(SDCARD_PIN_SPI0_MOSI, GPIO_FUNC_SPI);
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gpio_init(SDCARD_PIN_SPI0_CS);
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//gpio_pull_up(SDCARD_PIN_SPI0_CS);
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@ -129,15 +141,40 @@ void init_spi(void)
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/* chip _select invalid*/
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CS_HIGH();
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spi_init(spi0, CLK_SLOW);
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#ifndef SDCARD_PIO
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gpio_set_function(SDCARD_PIN_SPI0_SCK, GPIO_FUNC_SPI);
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gpio_set_function(SDCARD_PIN_SPI0_MISO, GPIO_FUNC_SPI);
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gpio_set_function(SDCARD_PIN_SPI0_MOSI, GPIO_FUNC_SPI);
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spi_init(SDCARD_SPI_BUS, CLK_SLOW);
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/* SPI0 parameter config */
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spi_set_format(spi0,
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spi_set_format(SDCARD_SPI_BUS,
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8, /* data_bits */
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SPI_CPOL_0, /* cpol */
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SPI_CPHA_0, /* cpha */
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SPI_MSB_FIRST /* order */
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);
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#else
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gpio_set_dir(SDCARD_PIN_SPI0_SCK, GPIO_OUT);
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gpio_set_dir(SDCARD_PIN_SPI0_MISO, GPIO_OUT);
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gpio_set_dir(SDCARD_PIN_SPI0_MOSI, GPIO_OUT);
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float clkdiv = 3.0f;
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int cpol = 0;
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int cpha = 0;
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uint cpha0_prog_offs = pio_add_program(pio_spi.pio, &spi_cpha0_program);
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pio_spi_init(pio_spi.pio, pio_spi.sm,
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cpha0_prog_offs,
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8, // 8 bits per SPI frame
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clkdiv,
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cpha,
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cpol,
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SDCARD_PIN_SPI0_SCK,
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SDCARD_PIN_SPI0_MOSI,
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SDCARD_PIN_SPI0_MISO
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);
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#endif
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}
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/* Exchange a byte */
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@ -147,7 +184,11 @@ BYTE xchg_spi (
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)
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{
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uint8_t *buff = (uint8_t *) &dat;
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spi_write_read_blocking(spi0, buff, buff, 1);
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#ifndef SDCARD_PIO
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spi_write_read_blocking(SDCARD_SPI_BUS, buff, buff, 1);
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#else
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pio_spi_write8_read8_blocking(&pio_spi, buff, buff, 1);
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#endif
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return (BYTE) *buff;
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}
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@ -160,7 +201,11 @@ void rcvr_spi_multi (
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)
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{
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uint8_t *b = (uint8_t *) buff;
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spi_read_blocking(spi0, 0xff, b, btr);
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#ifndef SDCARD_PIO
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spi_read_blocking(SDCARD_SPI_BUS, 0xff, b, btr);
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#else
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pio_spi_repeat8_read8_blocking(&pio_spi, 0xff, b, btr);
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#endif
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}
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@ -427,7 +472,11 @@ void xmit_spi_multi (
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)
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{
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const uint8_t *b = (const uint8_t *) buff;
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spi_write_blocking(spi0, b, btx);
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#ifndef SDCARD_PIO
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spi_write_blocking(SDCARD_SPI_BUS, b, btx);
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#else
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pio_spi_write8_blocking(&pio_spi, b, btx);
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#endif
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}
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/*-----------------------------------------------------------------------*/
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@ -1,10 +1,13 @@
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if (NOT TARGET sdcard)
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add_library(sdcard INTERFACE)
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pico_generate_pio_header(sdcard ${CMAKE_CURRENT_LIST_DIR}/spi.pio)
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target_sources(sdcard INTERFACE
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${CMAKE_CURRENT_LIST_DIR}/sdcard.c
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${CMAKE_CURRENT_LIST_DIR}/pio_spi.c
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)
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target_link_libraries(sdcard INTERFACE fatfs pico_stdlib hardware_clocks hardware_spi)
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target_link_libraries(sdcard INTERFACE fatfs pico_stdlib hardware_clocks hardware_spi hardware_pio)
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target_include_directories(sdcard INTERFACE ${CMAKE_CURRENT_LIST_DIR})
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endif()
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@ -4,6 +4,10 @@
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/* SPI pin assignment */
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/* Pico Wireless */
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#ifndef SDCARD_SPI_BUS
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#define SDCARD_SPI_BUS spi0
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#endif
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#ifndef SDCARD_PIN_SPI0_CS
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#define SDCARD_PIN_SPI0_CS 22
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#endif
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@ -0,0 +1,168 @@
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;
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; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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;
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; SPDX-License-Identifier: BSD-3-Clause
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;
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; These programs implement full-duplex SPI, with a SCK period of 4 clock
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; cycles. A different program is provided for each value of CPHA, and CPOL is
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; achieved using the hardware GPIO inversion available in the IO controls.
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;
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; Transmit-only SPI can go twice as fast -- see the ST7789 example!
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.program spi_cpha0
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.side_set 1
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; Pin assignments:
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; - SCK is side-set pin 0
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; - MOSI is OUT pin 0
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; - MISO is IN pin 0
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;
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; Autopush and autopull must be enabled, and the serial frame size is set by
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; configuring the push/pull threshold. Shift left/right is fine, but you must
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; justify the data yourself. This is done most conveniently for frame sizes of
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; 8 or 16 bits by using the narrow store replication and narrow load byte
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; picking behaviour of RP2040's IO fabric.
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; Clock phase = 0: data is captured on the leading edge of each SCK pulse, and
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; transitions on the trailing edge, or some time before the first leading edge.
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out pins, 1 side 0 [1] ; Stall here on empty (sideset proceeds even if
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in pins, 1 side 1 [1] ; instruction stalls, so we stall with SCK low)
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.program spi_cpha1
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.side_set 1
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; Clock phase = 1: data transitions on the leading edge of each SCK pulse, and
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; is captured on the trailing edge.
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out x, 1 side 0 ; Stall here on empty (keep SCK deasserted)
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mov pins, x side 1 [1] ; Output data, assert SCK (mov pins uses OUT mapping)
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in pins, 1 side 0 ; Input data, deassert SCK
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% c-sdk {
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#include "hardware/gpio.h"
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static inline void pio_spi_init(PIO pio, uint sm, uint prog_offs, uint n_bits,
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float clkdiv, bool cpha, bool cpol, uint pin_sck, uint pin_mosi, uint pin_miso) {
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pio_sm_config c = cpha ? spi_cpha1_program_get_default_config(prog_offs) : spi_cpha0_program_get_default_config(prog_offs);
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sm_config_set_out_pins(&c, pin_mosi, 1);
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sm_config_set_in_pins(&c, pin_miso);
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sm_config_set_sideset_pins(&c, pin_sck);
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// Only support MSB-first in this example code (shift to left, auto push/pull, threshold=nbits)
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sm_config_set_out_shift(&c, false, true, n_bits);
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sm_config_set_in_shift(&c, false, true, n_bits);
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sm_config_set_clkdiv(&c, clkdiv);
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// MOSI, SCK output are low, MISO is input
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pio_sm_set_pins_with_mask(pio, sm, 0, (1u << pin_sck) | (1u << pin_mosi));
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pio_sm_set_pindirs_with_mask(pio, sm, (1u << pin_sck) | (1u << pin_mosi), (1u << pin_sck) | (1u << pin_mosi) | (1u << pin_miso));
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pio_gpio_init(pio, pin_mosi);
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pio_gpio_init(pio, pin_miso);
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pio_gpio_init(pio, pin_sck);
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// The pin muxes can be configured to invert the output (among other things
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// and this is a cheesy way to get CPOL=1
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gpio_set_outover(pin_sck, cpol ? GPIO_OVERRIDE_INVERT : GPIO_OVERRIDE_NORMAL);
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// SPI is synchronous, so bypass input synchroniser to reduce input delay.
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hw_set_bits(&pio->input_sync_bypass, 1u << pin_miso);
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pio_sm_init(pio, sm, prog_offs, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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; SPI with Chip Select
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; -----------------------------------------------------------------------------
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;
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; For your amusement, here are some SPI programs with an automatic chip select
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; (asserted once data appears in TX FIFO, deasserts when FIFO bottoms out, has
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; a nice front/back porch).
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;
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; The number of bits per FIFO entry is configured via the Y register
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; and the autopush/pull threshold. From 2 to 32 bits.
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;
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; Pin assignments:
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; - SCK is side-set bit 0
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; - CSn is side-set bit 1
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; - MOSI is OUT bit 0 (host-to-device)
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; - MISO is IN bit 0 (device-to-host)
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;
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; This program only supports one chip select -- use GPIO if more are needed
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;
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; Provide a variation for each possibility of CPHA; for CPOL we can just
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; invert SCK in the IO muxing controls (downstream from PIO)
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; CPHA=0: data is captured on the leading edge of each SCK pulse (including
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; the first pulse), and transitions on the trailing edge
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.program spi_cpha0_cs
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.side_set 2
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.wrap_target
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bitloop:
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out pins, 1 side 0x0 [1]
|
||||
in pins, 1 side 0x1
|
||||
jmp x-- bitloop side 0x1
|
||||
|
||||
out pins, 1 side 0x0
|
||||
mov x, y side 0x0 ; Reload bit counter from Y
|
||||
in pins, 1 side 0x1
|
||||
jmp !osre bitloop side 0x1 ; Fall-through if TXF empties
|
||||
|
||||
nop side 0x0 [1] ; CSn back porch
|
||||
public entry_point: ; Must set X,Y to n-2 before starting!
|
||||
pull ifempty side 0x2 [1] ; Block with CSn high (minimum 2 cycles)
|
||||
.wrap ; Note ifempty to avoid time-of-check race
|
||||
|
||||
; CPHA=1: data transitions on the leading edge of each SCK pulse, and is
|
||||
; captured on the trailing edge
|
||||
|
||||
.program spi_cpha1_cs
|
||||
.side_set 2
|
||||
|
||||
.wrap_target
|
||||
bitloop:
|
||||
out pins, 1 side 0x1 [1]
|
||||
in pins, 1 side 0x0
|
||||
jmp x-- bitloop side 0x0
|
||||
|
||||
out pins, 1 side 0x1
|
||||
mov x, y side 0x1
|
||||
in pins, 1 side 0x0
|
||||
jmp !osre bitloop side 0x0
|
||||
|
||||
public entry_point: ; Must set X,Y to n-2 before starting!
|
||||
pull ifempty side 0x2 [1] ; Block with CSn high (minimum 2 cycles)
|
||||
nop side 0x0 [1]; CSn front porch
|
||||
.wrap
|
||||
|
||||
% c-sdk {
|
||||
#include "hardware/gpio.h"
|
||||
static inline void pio_spi_cs_init(PIO pio, uint sm, uint prog_offs, uint n_bits, float clkdiv, bool cpha, bool cpol,
|
||||
uint pin_sck, uint pin_mosi, uint pin_miso) {
|
||||
pio_sm_config c = cpha ? spi_cpha1_cs_program_get_default_config(prog_offs) : spi_cpha0_cs_program_get_default_config(prog_offs);
|
||||
sm_config_set_out_pins(&c, pin_mosi, 1);
|
||||
sm_config_set_in_pins(&c, pin_miso);
|
||||
sm_config_set_sideset_pins(&c, pin_sck);
|
||||
sm_config_set_out_shift(&c, false, true, n_bits);
|
||||
sm_config_set_in_shift(&c, false, true, n_bits);
|
||||
sm_config_set_clkdiv(&c, clkdiv);
|
||||
|
||||
pio_sm_set_pins_with_mask(pio, sm, (2u << pin_sck), (3u << pin_sck) | (1u << pin_mosi));
|
||||
pio_sm_set_pindirs_with_mask(pio, sm, (3u << pin_sck) | (1u << pin_mosi), (3u << pin_sck) | (1u << pin_mosi) | (1u << pin_miso));
|
||||
pio_gpio_init(pio, pin_mosi);
|
||||
pio_gpio_init(pio, pin_miso);
|
||||
pio_gpio_init(pio, pin_sck);
|
||||
pio_gpio_init(pio, pin_sck + 1);
|
||||
gpio_set_outover(pin_sck, cpol ? GPIO_OVERRIDE_INVERT : GPIO_OVERRIDE_NORMAL);
|
||||
hw_set_bits(&pio->input_sync_bypass, 1u << pin_miso);
|
||||
|
||||
uint entry_point = prog_offs + (cpha ? spi_cpha1_cs_offset_entry_point : spi_cpha0_cs_offset_entry_point);
|
||||
pio_sm_init(pio, sm, entry_point, &c);
|
||||
pio_sm_exec(pio, sm, pio_encode_set(pio_x, n_bits - 2));
|
||||
pio_sm_exec(pio, sm, pio_encode_set(pio_y, n_bits - 2));
|
||||
pio_sm_set_enabled(pio, sm, true);
|
||||
}
|
||||
%}
|
||||
Ładowanie…
Reference in New Issue