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Implemented PAL interrupt driver for VSYNC interrupt

pull/1/head
Sven Steudte 2018-02-09 03:47:11 +01:00
rodzic 07fccb5f32
commit bc71efd6aa
2 zmienionych plików z 14 dodań i 21 usunięć
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21
tracker/software/drivers/ov5640.c
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@ -918,8 +918,10 @@ static void dma_interrupt(void *p, uint32_t flags) {
* VSYNC is asserted during a frame. * VSYNC is asserted during a frame.
* See OV5640 datasheet for details. * See OV5640 datasheet for details.
*/ */
CH_IRQ_HANDLER(Vector9C) { void vsync_cb(void *arg) {
CH_IRQ_PROLOGUE(); (void)arg;
chSysLockFromISR();
// VSYNC handling // VSYNC handling
if(!vsync) { if(!vsync) {
@ -946,12 +948,11 @@ CH_IRQ_HANDLER(Vector9C) {
* Disable VSYNC edge interrupts. * Disable VSYNC edge interrupts.
* Flag image capture complete. * Flag image capture complete.
*/ */
nvicDisableVector(EXTI1_IRQn); palDisableLineEventI(LINE_CAM_VSYNC);
capture_finished = true; capture_finished = true;
} }
EXTI->PR |= EXTI_PR_PR1; chSysUnlockFromISR();
CH_IRQ_EPILOGUE();
} }
bool OV5640_Capture(uint8_t* buffer, uint32_t size) bool OV5640_Capture(uint8_t* buffer, uint32_t size)
@ -1055,13 +1056,11 @@ bool OV5640_Capture(uint8_t* buffer, uint32_t size)
while(!palReadLine(LINE_CAM_VSYNC)); // Wait for current picture to finish transmission while(!palReadLine(LINE_CAM_VSYNC)); // Wait for current picture to finish transmission
// Setup EXTI: EXTI5 PC for PC5 (VSYNC) // Enable VSYNC interrupt
SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PC; palSetLineCallback(LINE_CAM_VSYNC, (palcallback_t)vsync_cb, NULL);
EXTI->IMR = EXTI_IMR_MR5; // Activate interrupt for chan5 (=>PC5) palEnableLineEvent(LINE_CAM_VSYNC, PAL_EVENT_MODE_RISING_EDGE);
EXTI->RTSR = EXTI_RTSR_TR5; // Listen on rising edge
nvicEnableVector(EXTI9_5_IRQn, 1); // Enable interrupt
// Capture // Wait for capture to be finished
do { do {
chThdSleep(TIME_MS2I(10)); chThdSleep(TIME_MS2I(10));
} while(!capture_finished && !dma_error); } while(!capture_finished && !dma_error);

14
tracker/software/mcuconf.h
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@ -39,14 +39,14 @@
* HAL driver system settings. * HAL driver system settings.
*/ */
#define STM32_NO_INIT FALSE #define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED FALSE #define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE #define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE #define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE #define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL #define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE #define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLM_VALUE 26 #define STM32_PLLM_VALUE 16
#define STM32_PLLN_VALUE 384 #define STM32_PLLN_VALUE 384
#define STM32_PLLP_VALUE 8 #define STM32_PLLP_VALUE 8
#define STM32_PLLQ_VALUE 8 #define STM32_PLLQ_VALUE 8
@ -66,12 +66,6 @@
#define STM32_PLS STM32_PLS_LEV0 #define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE #define STM32_BKPRAM_ENABLE FALSE
/*
* PAL driver system settings.
*/
//#define STM32_DISABLE_EXTI1_HANDLER
#define STM32_DISABLE_EXTI5_9_HANDLER
/* /*
* ADC driver system settings. * ADC driver system settings.
*/ */