mirror
/
pecanpico10
kopia lustrzana https://github.com/DL7AD/pecanpico10
1
0
Forkuj 0
Kod Zgłoszenia Projekty Wydania Wiki Aktywność

Fixed image sampling (stage 1, working, not finished yet)

pull/1/head
Sven Steudte 2018-02-11 05:42:17 +01:00
rodzic bc71efd6aa
commit 2f68054525
6 zmienionych plików z 651 dodań i 659 usunięć
Pokaż statystyki Ściągnij plik aktualizacji Ściągnij plik porównania Expand all files Collapse all files

2
tracker/software/Makefile
Wyświetl plik

@ -66,7 +66,7 @@ endif
# Stack size to the allocated to the Cortex-M main/exceptions stack. This
# stack is used for processing interrupts and exceptions.
ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x1000
USE_EXCEPTIONS_STACKSIZE = 0x1500
endif
# Enables the use of FPU (no, softfp, hard).

17
tracker/software/config.c
Wyświetl plik

@ -7,7 +7,7 @@ conf_t config = {
// Primary position transmission thread
.pos_pri = {
.thread_conf = {
.active = true,
.active = false,
.cycle = TIME_S2I(120)
},
.radio_conf = {
@ -47,8 +47,9 @@ conf_t config = {
// Primary image transmission thread
.img_pri = {
.thread_conf = {
.active = false,
.cycle = CYCLE_CONTINUOUSLY
.active = true,
.cycle = CYCLE_CONTINUOUSLY,
.init_delay = TIME_S2I(5)
},
.radio_conf = {
.pwr = 0x7F,
@ -60,9 +61,9 @@ conf_t config = {
.call = "DL7AD-12",
.path = "",
.res = RES_QVGA,
.res = RES_VGA,
.quality = 4,
.buf_size = 32*1024
.buf_size = 64*1024
},
// Secondary image transmission thread
@ -104,7 +105,7 @@ conf_t config = {
},
.rx = {
.thread_conf = {
.active = true
.active = false
},
.radio_conf = {
.pwr = 0x7F,
@ -113,8 +114,8 @@ conf_t config = {
.preamble = 200
},
.call = "VK2GJ-15",
.path = "WIDE2-1",
.call = "DL7AD-12",
.path = "WIDE1-1",
.symbol = SYM_DIGIPEATER
},

693
tracker/software/drivers/ov5640.c
Wyświetl plik

@ -70,8 +70,8 @@ static const struct regval_list OV5640YUV_Sensor_Dvp_Init[] =
{ 0x3c0a, 0x9c },
{ 0x3c0b, 0x40 },
{ 0x3820, 0x47 },
{ 0x3821, 0x00 }, //07
{ 0x3820, 0x41 },
{ 0x3821, 0x01 }, //07
//windows setup
{ 0x3800, 0x00 },
@ -319,7 +319,7 @@ static const struct regval_list OV5640YUV_Sensor_Dvp_Init[] =
{ 0x3406, 0x00 },//awbinit
{ 0x3503, 0x00 },//awbinit
{ 0x3008, 0x02 },
{ 0xffff, 0xff },
{ 0xffff, 0xff },
};
@ -327,328 +327,297 @@ static const struct regval_list OV5640YUV_Sensor_Dvp_Init[] =
//2592x1944 QSXGA
static const struct regval_list OV5640_JPEG_QSXGA[] =
{
{0x3820, 0x47},
{0x3821, 0x20},
{0x3814, 0x11},
{0x3815, 0x11},
{0x3803, 0x00},
{0x3807, 0x9f},
{0x3808, 0x0a},
{0x3809, 0x20},
{0x380a, 0x07},
{0x380b, 0x98},
{0x380c, 0x0b},
{0x380d, 0x1c},
{0x380e, 0x07},
{0x380f, 0xb0},
{0x3813, 0x04},
{0x3618, 0x04},
{0x3612, 0x4b},
{0x3708, 0x64},
{0x3709, 0x12},
{0x370c, 0x00},
{0x3a02, 0x07},
{0x3a03, 0xb0},
{0x3a0e, 0x06},
{0x3a0d, 0x08},
{0x3a14, 0x07},
{0x3a15, 0xb0},
{0x4001, 0x02},
{0x4004, 0x06},
{0x3002, 0x00},
{0x3006, 0xff},
{0x3824, 0x04},
{0x5001, 0x83},
{0x3036, 0x69},
{0x3035, 0x31},
{0x4005, 0x1A},
{0xffff, 0xff},
{0x3820 ,0x40},
{0x3821 ,0x26},
{0x3814 ,0x11},
{0x3815 ,0x11},
{0x3803 ,0x00},
{0x3807 ,0x9f},
{0x3808 ,0x0a},
{0x3809 ,0x20},
{0x380a ,0x07},
{0x380b ,0x98},
{0x380c ,0x0b},
{0x380d ,0x1c},
{0x380e ,0x07},
{0x380f ,0xb0},
{0x3813 ,0x04},
{0x3618 ,0x04},
{0x3612 ,0x4b},
{0x3708 ,0x64},
{0x3709 ,0x12},
{0x370c ,0x00},
{0x3a02 ,0x07},
{0x3a03 ,0xb0},
{0x3a0e ,0x06},
{0x3a0d ,0x08},
{0x3a14 ,0x07},
{0x3a15 ,0xb0},
{0x4001 ,0x02},
{0x4004 ,0x06},
{0x3002 ,0x00},
{0x3006 ,0xff},
{0x3824 ,0x04},
{0x5001 ,0x83},
{0x3036 ,0x69},
{0x3035 ,0x31},
{0x4005 ,0x1A},
{0xffff, 0xff},
};
//5MP
static const struct regval_list OV5640_5MP_JPEG[] =
{
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0xA },
{0x3805, 0x3f},
{0x3806, 0x7 },
{0x3807, 0x9f},
{0x3808, 0xA },
{0x3809, 0x20},
{0x380a, 0x7 },
{0x380b, 0x98},
{0x380c, 0xc },
{0x380d, 0x80},
{0x380e, 0x7 },
{0x380f, 0xd0},
{0x5001, 0xa3},
{0x5680, 0x0 },
{0x5681, 0x0 },
{0x5682, 0xA },
{0x5683, 0x20},
{0x5684, 0x0 },
{0x5685, 0x0 },
{0x5686, 0x7 },
{0x5687, 0x98},
{0x3800 ,0x00},
{0x3801 ,0x00},
{0x3802 ,0x00},
{0x3803 ,0x00},
{0x3804 ,0xA },
{0x3805 ,0x3f},
{0x3806 ,0x7 },
{0x3807 ,0x9f},
{0x3808 ,0xA },
{0x3809 ,0x20},
{0x380a ,0x7 },
{0x380b ,0x98},
{0x380c ,0xc },
{0x380d ,0x80},
{0x380e ,0x7 },
{0x380f ,0xd0},
{0x5001 ,0xa3},
{0x5680 ,0x0 },
{0x5681 ,0x0 },
{0x5682 ,0xA },
{0x5683 ,0x20},
{0x5684 ,0x0 },
{0x5685 ,0x0 },
{0x5686 ,0x7 },
{0x5687 ,0x98},
{0xffff, 0xff},
};
//320x240 QVGA
static const struct regval_list OV5640_QSXGA2QVGA[] =
{
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0xA },
{0x3805, 0x3f},
{0x3806, 0x7 },
{0x3807, 0x9f},
{0x3808, 0x1 },
{0x3809, 0x40},
{0x380a, 0x0 },
{0x380b, 0xf0},
{0x380c, 0xc },
{0x380d, 0x80},
{0x380e, 0x7 },
{0x380f, 0xd0},
{0x5001, 0xa3},
{0x5680, 0x0 },
{0x5681, 0x0 },
{0x5682, 0xA },
{0x5683, 0x20},
{0x5684, 0x0 },
{0x5685, 0x0 },
{0x5686, 0x7 },
{0x5687, 0x98},
{0x3800 ,0x00},
{0x3801 ,0x00},
{0x3802 ,0x00},
{0x3803 ,0x00},
{0x3804 ,0xA },
{0x3805 ,0x3f},
{0x3806 ,0x7 },
{0x3807 ,0x9f},
{0x3808 ,0x1 },
{0x3809 ,0x40},
{0x380a ,0x0 },
{0x380b ,0xf0},
{0x380c ,0xc },
{0x380d ,0x80},
{0x380e ,0x7 },
{0x380f ,0xd0},
{0x5001 ,0xa3},
{0x5680 ,0x0 },
{0x5681 ,0x0 },
{0x5682 ,0xA },
{0x5683 ,0x20},
{0x5684 ,0x0 },
{0x5685 ,0x0 },
{0x5686 ,0x7 },
{0x5687 ,0x98},
{0xffff, 0xff},
};
//320x240 QQVGA
static const struct regval_list OV5640_QSXGA2QQVGA[] =
{
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0xA },
{0x3805, 0x3f},
{0x3806, 0x7 },
{0x3807, 0x9f},
{0x3808, 0x0 },
{0x3809, 0xA0},
{0x380a, 0x0 },
{0x380b, 0x70},
{0x380c, 0xc },
{0x380d, 0x80},
{0x380e, 0x7 },
{0x380f, 0xd0},
{0x5001, 0xa3},
{0x5680, 0x0 },
{0x5681, 0x0 },
{0x5682, 0xA },
{0x5683, 0x20},
{0x5684, 0x0 },
{0x5685, 0x0 },
{0x5686, 0x7 },
{0x5687, 0x98},
{0x3800 ,0x00},
{0x3801 ,0x00},
{0x3802 ,0x00},
{0x3803 ,0x00},
{0x3804 ,0xA },
{0x3805 ,0x3f},
{0x3806 ,0x7 },
{0x3807 ,0x9f},
{0x3808 ,0x0 },
{0x3809 ,0xA0},
{0x380a ,0x0 },
{0x380b ,0x70},
{0x380c ,0xc },
{0x380d ,0x80},
{0x380e ,0x7 },
{0x380f ,0xd0},
{0x5001 ,0xa3},
{0x5680 ,0x0 },
{0x5681 ,0x0 },
{0x5682 ,0xA },
{0x5683 ,0x20},
{0x5684 ,0x0 },
{0x5685 ,0x0 },
{0x5686 ,0x7 },
{0x5687 ,0x98},
{0xffff, 0xff},
};
//640x480 VGA
static const struct regval_list OV5640_QSXGA2VGA[] =
{
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0xA },
{0x3805, 0x3f},
{0x3806, 0x7 },
{0x3807, 0x9f},
{0x3808, 0x2 },
{0x3809, 0x80},
{0x380a, 0x1 },
{0x380b, 0xe0},
{0x380c, 0xc },
{0x380d, 0x80},
{0x380e, 0x7 },
{0x380f, 0xd0},
{0x5001, 0xa3},
{0x5680, 0x0 },
{0x5681, 0x0 },
{0x5682, 0xA },
{0x5683, 0x20},
{0x5684, 0x0 },
{0x5685, 0x0 },
{0x5686, 0x7 },
{0x5687, 0x98},
{0xffff, 0xff},
};
//640x480 VGA
static const struct regval_list OV5640_QSXGA2VGA_ZOOMED[] =
{
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0xA },
{0x3805, 0x3f},
{0x3806, 0x7 },
{0x3807, 0x9f},
{0x3808, 0x2 },
{0x3809, 0x80},
{0x380a, 0x1 },
{0x380b, 0xe0},
{0x380c, 0xc },
{0x380d, 0x80},
{0x380e, 0x7 },
{0x380f, 0xd0},
{0x5001, 0xa3},
{0x5680, 0x0 },
{0x5681, 0x0 },
{0x5682, 0xA },
{0x5683, 0x20},
{0x5684, 0x0 },
{0x5685, 0x0 },
{0x5686, 0x7 },
{0x5687, 0x98},
{0xffff, 0xff},
{0x3800 ,0x00},
{0x3801 ,0x00},
{0x3802 ,0x00},
{0x3803 ,0x00},
{0x3804 ,0xA },
{0x3805 ,0x3f},
{0x3806 ,0x7 },
{0x3807 ,0x9f},
{0x3808 ,0x2 },
{0x3809 ,0x80},
{0x380a ,0x1 },
{0x380b ,0xe0},
{0x380c ,0xc },
{0x380d ,0x80},
{0x380e ,0x7 },
{0x380f ,0xd0},
{0x5001 ,0xa3},
{0x5680 ,0x0 },
{0x5681 ,0x0 },
{0x5682 ,0xA },
{0x5683 ,0x20},
{0x5684 ,0x0 },
{0x5685 ,0x0 },
{0x5686 ,0x7 },
{0x5687 ,0x98},
{0xffff, 0xff},
};
//800x480 WVGA
static const struct regval_list OV5640_QSXGA2WVGA[] =
{
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0xA },
{0x3805, 0x3f},
{0x3806, 0x7 },
{0x3807, 0x9f},
{0x3808, 0x3 },
{0x3809, 0x20},
{0x380a, 0x1 },
{0x380b, 0xe0},
{0x380c, 0xc },
{0x380d, 0x80},
{0x380e, 0x7 },
{0x380f, 0xd0},
{0x3800 ,0x00},
{0x3801 ,0x00},
{0x3802 ,0x00},
{0x3803 ,0x00},
{0x3804 ,0xA },
{0x3805 ,0x3f},
{0x3806 ,0x7 },
{0x3807 ,0x9f},
{0x3808 ,0x3 },
{0x3809 ,0x20},
{0x380a ,0x1 },
{0x380b ,0xe0},
{0x380c ,0xc },
{0x380d ,0x80},
{0x380e ,0x7 },
{0x380f ,0xd0},
{0x3810, 0x00},
{0x3811, 0x10},
{0x3812, 0x01},
{0x3813, 0x48},
{0x5001, 0xa3},
{0x5680, 0x0 },
{0x5681, 0x0 },
{0x5682, 0xA },
{0x5683, 0x20},
{0x5684, 0x0 },
{0x5685, 0x0 },
{0x5686, 0x7 },
{0x5687, 0x98},
{0x5001 ,0xa3},
{0x5680 ,0x0 },
{0x5681 ,0x0 },
{0x5682 ,0xA },
{0x5683 ,0x20},
{0x5684 ,0x0 },
{0x5685 ,0x0 },
{0x5686 ,0x7 },
{0x5687 ,0x98},
{0xffff, 0xff},
};
//352x288 CIF
static const struct regval_list OV5640_QSXGA2CIF[] =
{
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0xA },
{0x3805, 0x3f},
{0x3806, 0x7 },
{0x3807, 0x9f},
{0x3808, 0x1 },
{0x3809, 0x60},
{0x380a, 0x1 },
{0x380b, 0x20},
{0x380c, 0xc },
{0x380d, 0x80},
{0x380e, 0x7 },
{0x380f, 0xd0},
{0x3800 ,0x00},
{0x3801 ,0x00},
{0x3802 ,0x00},
{0x3803 ,0x00},
{0x3804 ,0xA },
{0x3805 ,0x3f},
{0x3806 ,0x7 },
{0x3807 ,0x9f},
{0x3808 ,0x1 },
{0x3809 ,0x60},
{0x380a ,0x1 },
{0x380b ,0x20},
{0x380c ,0xc },
{0x380d ,0x80},
{0x380e ,0x7 },
{0x380f ,0xd0},
{0x3810, 0x00},
{0x3811, 0x10},
{0x3812, 0x00},
{0x3813, 0x70},
{0x5001, 0xa3},
{0x5680, 0x0 },
{0x5681, 0x0 },
{0x5682, 0xA },
{0x5683, 0x20},
{0x5684, 0x0 },
{0x5685, 0x0 },
{0x5686, 0x7 },
{0x5687, 0x98},
{0x5001 ,0xa3},
{0x5680 ,0x0 },
{0x5681 ,0x0 },
{0x5682 ,0xA },
{0x5683 ,0x20},
{0x5684 ,0x0 },
{0x5685 ,0x0 },
{0x5686 ,0x7 },
{0x5687 ,0x98},
{0xffff, 0xff},
};
//1280x960 SXGA
static const struct regval_list OV5640_QSXGA2SXGA[] =
{
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0xA },
{0x3805, 0x3f},
{0x3806, 0x7 },
{0x3807, 0x9f},
{0x3808, 0x5 },
{0x3809, 0x0 },
{0x380a, 0x3 },
{0x380b, 0xc0},
{0x380c, 0xc },
{0x380d, 0x80},
{0x380e, 0x7 },
{0x380f, 0xd0},
{0x5001, 0xa3},
{0x5680, 0x0 },
{0x5681, 0x0 },
{0x5682, 0xA },
{0x5683, 0x20},
{0x5684, 0x0 },
{0x5685, 0x0 },
{0x5686, 0x7 },
{0x5687, 0x98},
{0x3800 ,0x00},
{0x3801 ,0x00},
{0x3802 ,0x00},
{0x3803 ,0x00},
{0x3804 ,0xA },
{0x3805 ,0x3f},
{0x3806 ,0x7 },
{0x3807 ,0x9f},
{0x3808 ,0x5 },
{0x3809 ,0x0 },
{0x380a ,0x3 },
{0x380b ,0xc0},
{0x380c ,0xc },
{0x380d ,0x80},
{0x380e ,0x7 },
{0x380f ,0xd0},
{0x5001 ,0xa3},
{0x5680 ,0x0 },
{0x5681 ,0x0 },
{0x5682 ,0xA },
{0x5683 ,0x20},
{0x5684 ,0x0 },
{0x5685 ,0x0 },
{0x5686 ,0x7 },
{0x5687 ,0x98},
{0xffff, 0xff},
};
//2048x1536 QXGA
static const struct regval_list OV5640_QSXGA2QXGA[] =
{
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0xA },
{0x3805, 0x3f},
{0x3806, 0x7 },
{0x3807, 0x9f},
{0x3808, 0x8 },
{0x3809, 0x0 },
{0x380a, 0x6 },
{0x380b, 0x0 },
{0x380c, 0xc },
{0x380d, 0x80},
{0x380e, 0x7 },
{0x380f, 0xd0},
{0x5001, 0xa3},
{0x5680, 0x0 },
{0x5681, 0x0 },
{0x5682, 0xA },
{0x5683, 0x20},
{0x5684, 0x0 },
{0x5685, 0x0 },
{0x5686, 0x7 },
{0x5687, 0x98},
{0x3800 ,0x00},
{0x3801 ,0x00},
{0x3802 ,0x00},
{0x3803 ,0x00},
{0x3804 ,0xA },
{0x3805 ,0x3f},
{0x3806 ,0x7 },
{0x3807 ,0x9f},
{0x3808 ,0x8 },
{0x3809 ,0x0 },
{0x380a ,0x6 },
{0x380b ,0x0 },
{0x380c ,0xc },
{0x380d ,0x80},
{0x380e ,0x7 },
{0x380f ,0xd0},
{0x5001 ,0xa3},
{0x5680 ,0x0 },
{0x5681 ,0x0 },
{0x5682 ,0xA },
{0x5683 ,0x20},
{0x5684 ,0x0 },
{0x5685 ,0x0 },
{0x5686 ,0x7 },
{0x5687 ,0x98},
{0xffff, 0xff},
};
@ -656,68 +625,68 @@ static const struct regval_list OV5640_QSXGA2QXGA[] =
//1600x1200 UXGA
static const struct regval_list OV5640_QSXGA2UXGA[] =
{
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0xA },
{0x3805, 0x3f},
{0x3806, 0x7 },
{0x3807, 0x9f},
{0x3808, 0x6 },
{0x3809, 0x40},
{0x380a, 0x4 },
{0x380b, 0xb0},
{0x380c, 0xc },
{0x380d, 0x80},
{0x380e, 0x7 },
{0x380f, 0xd0},
{0x5001, 0xa3},
{0x5680, 0x0 },
{0x5681, 0x0 },
{0x5682, 0xA },
{0x5683, 0x20},
{0x5684, 0x0 },
{0x5685, 0x0 },
{0x5686, 0x7 },
{0x5687, 0x98},
{0x3800 ,0x00},
{0x3801 ,0x00},
{0x3802 ,0x00},
{0x3803 ,0x00},
{0x3804 ,0xA },
{0x3805 ,0x3f},
{0x3806 ,0x7 },
{0x3807 ,0x9f},
{0x3808 ,0x6 },
{0x3809 ,0x40},
{0x380a ,0x4 },
{0x380b ,0xb0},
{0x380c ,0xc },
{0x380d ,0x80},
{0x380e ,0x7 },
{0x380f ,0xd0},
{0x5001 ,0xa3},
{0x5680 ,0x0 },
{0x5681 ,0x0 },
{0x5682 ,0xA },
{0x5683 ,0x20},
{0x5684 ,0x0 },
{0x5685 ,0x0 },
{0x5686 ,0x7 },
{0x5687 ,0x98},
{0xffff, 0xff},
};
//1024x768 XGA
static const struct regval_list OV5640_QSXGA2XGA[] =
{
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0xA },
{0x3805, 0x3f},
{0x3806, 0x7 },
{0x3807, 0x9f},
{0x3808, 0x4 },
{0x3809, 0x0 },
{0x380a, 0x3 },
{0x380b, 0x0 },
{0x380c, 0xc },
{0x380d, 0x80},
{0x380e, 0x7 },
{0x380f, 0xd0},
{0x5001, 0xa3},
{0x5680, 0x0 },
{0x5681, 0x0 },
{0x5682, 0xA },
{0x5683, 0x20},
{0x5684, 0x0 },
{0x5685, 0x0 },
{0x5686, 0x7 },
{0x5687, 0x98},
{0x3800 ,0x00},
{0x3801 ,0x00},
{0x3802 ,0x00},
{0x3803 ,0x00},
{0x3804 ,0xA },
{0x3805 ,0x3f},
{0x3806 ,0x7 },
{0x3807 ,0x9f},
{0x3808 ,0x4 },
{0x3809 ,0x0 },
{0x380a ,0x3 },
{0x380b ,0x0 },
{0x380c ,0xc },
{0x380d ,0x80},
{0x380e ,0x7 },
{0x380f ,0xd0},
{0x5001 ,0xa3},
{0x5680 ,0x0 },
{0x5681 ,0x0 },
{0x5682 ,0xA },
{0x5683 ,0x20},
{0x5684 ,0x0 },
{0x5685 ,0x0 },
{0x5686 ,0x7 },
{0x5687 ,0x98},
{0xffff, 0xff},
};
// TODO: Implement a state machine instead of multiple flags
static bool capture_finished;
static bool vsync;
static bool dma_error;
static uint32_t dma_flags;
@ -749,8 +718,7 @@ uint32_t OV5640_Snapshot2RAM(uint8_t* buffer, uint32_t size, resolution_t res)
// Capture image until we get a good image (max 10 tries)
do {
// Clearing buffer
uint32_t i;
for(i=0; i<size; i++)
for(uint32_t i=0; i<size; i++)
buffer[i] = 0;
TRACE_INFO("CAM > Capture image");
@ -761,6 +729,14 @@ uint32_t OV5640_Snapshot2RAM(uint8_t* buffer, uint32_t size, resolution_t res)
while(!buffer[size_sampled] && size_sampled > 0)
size_sampled--;
for(uint32_t i=0; i<(size_sampled+31)/32; i++) {
TRACE_DEBUG("0x%04x > %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
i*32, buffer[i*32+0 ], buffer[i*32+1 ], buffer[i*32+2 ], buffer[i*32+3 ], buffer[i*32+4 ], buffer[i*32+5 ], buffer[i*32+6 ], buffer[i*32+7 ],
buffer[i*32+8 ], buffer[i*32+9 ], buffer[i*32+10], buffer[i*32+11], buffer[i*32+12], buffer[i*32+13], buffer[i*32+14], buffer[i*32+15],
buffer[i*32+16], buffer[i*32+17], buffer[i*32+18], buffer[i*32+19], buffer[i*32+20], buffer[i*32+21], buffer[i*32+22], buffer[i*32+23],
buffer[i*32+24], buffer[i*32+25], buffer[i*32+26], buffer[i*32+27], buffer[i*32+28], buffer[i*32+29], buffer[i*32+30], buffer[i*32+31]);
}
TRACE_INFO("CAM > Image size: %d bytes", size_sampled);
} while(!status && cntr--);
@ -772,7 +748,7 @@ const stm32_dma_stream_t *dmastp;
#if OV5640_USE_DMA_DBM == TRUE
uint16_t dma_index;
uint16_t dma_buffers;
#define DMA_SEGMENT_SIZE 1024
#define DMA_SEGMENT_SIZE 65535
#define DMA_FIFO_BURST_ALIGN 32
@ -828,6 +804,7 @@ static void dma_interrupt(void *p, uint32_t flags) {
* Disable timer DMA request and flag fault.
*/
TIM8->DIER &= ~TIM_DIER_CC1DE;
dma_stop();
dma_error = true;
dmaStreamClearInterrupt(dmastp);
return;
@ -850,6 +827,7 @@ static void dma_interrupt(void *p, uint32_t flags) {
*/
TIM8->DIER &= ~TIM_DIER_CC1DE;
dma_stop();
dma_error = true;
dmaStreamClearInterrupt(dmastp);
return;
@ -869,8 +847,7 @@ static void dma_interrupt(void *p, uint32_t flags) {
* DMA will use new address at h/w DBM switch.
*/
if (dmaStreamGetCurrentTarget(dmastp) == 1) {
if(dmaStreamGetCurrentTarget(dmastp) == 1) {
dmaStreamSetMemory0(dmastp, &dma_buffer[++dma_index * DMA_SEGMENT_SIZE]);
} else {
dmaStreamSetMemory1(dmastp, &dma_buffer[++dma_index * DMA_SEGMENT_SIZE]);
@ -886,14 +863,15 @@ static void dma_interrupt(void *p, uint32_t flags) {
(void)p;
dma_flags = flags;
dmaStreamClearInterrupt(dmastp);
if(flags & (STM32_DMA_ISR_FEIF | STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) {
/*
* DMA transfer error, FIFO error or Direct mode error.
* See 9.34.19 of RM0430.
*/
dmaStreamClearInterrupt(dmastp);
TIM8->DIER &= ~TIM_DIER_CC1DE;
dma_stop();
dma_error = true;
return;
}
@ -907,9 +885,11 @@ static void dma_interrupt(void *p, uint32_t flags) {
* Dont stop the DMA here. Its going to be stopped by the leading edge of VSYNC.
*/
TIM8->DIER &= ~TIM_DIER_CC1DE;
dma_stop();
dma_error = true;
return;
}
dmaStreamClearInterrupt(dmastp);
}
#endif /* USE_OV5640_DMA_DBM */
@ -918,13 +898,14 @@ static void dma_interrupt(void *p, uint32_t flags) {
* VSYNC is asserted during a frame.
* See OV5640 datasheet for details.
*/
static uint8_t vsync_cntr;
void vsync_cb(void *arg) {
(void)arg;
chSysLockFromISR();
// VSYNC handling
if(!vsync) {
if(!vsync_cntr) {
/*
* Rising edge of VSYNC after TIM8 has been initialised.
* Start DMA channel.
@ -932,7 +913,7 @@ void vsync_cb(void *arg) {
*/
dma_start();
TIM8->DIER |= TIM_DIER_CC1DE;
vsync = true;
vsync_cntr++;
} else {
/* VSYNC leading with vsync true.
* This means end of capture for the frame.
@ -958,7 +939,7 @@ void vsync_cb(void *arg) {
bool OV5640_Capture(uint8_t* buffer, uint32_t size)
{
OV5640_setLightIntensity();
TRACE_DEBUG("A buffer_addr=%08x", buffer);chThdSleep(TIME_MS2I(10));
/*
* Note:
* If there are no Chibios devices enabled that use DMA then...
@ -966,6 +947,9 @@ bool OV5640_Capture(uint8_t* buffer, uint32_t size)
* UDEFS = -DSTM32_DMA_REQUIRED
*/
TRACE_DEBUG("E");chThdSleep(TIME_MS2I(10));
I2C_Lock(); // Lock I2C because it uses the same DMA
/* Setup DMA for transfer on TIM8_CH1 - DMA2 stream 2, channel 7 */
dmastp = STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 2));
uint32_t dmamode = STM32_DMA_CR_CHSEL(7) |
@ -989,7 +973,7 @@ bool OV5640_Capture(uint8_t* buffer, uint32_t size)
#if OV5640_USE_DMA_DBM == TRUE
dma_buffer = buffer;
TRACE_DEBUG("B");chThdSleep(TIME_MS2I(10));
/*
* Buffer address must be word aligned.
* Also note requirement for burst transfers from FIFO.
@ -1011,7 +995,7 @@ bool OV5640_Capture(uint8_t* buffer, uint32_t size)
dmaStreamSetMemory0(dmastp, &buffer[0]);
dmaStreamSetMemory1(dmastp, &buffer[DMA_SEGMENT_SIZE]);
dmaStreamSetTransactionSize(dmastp, DMA_SEGMENT_SIZE);
TRACE_DEBUG("C");chThdSleep(TIME_MS2I(10));
/*
* Calculate the number of whole buffers.
* TODO: Make this include remainder memory as partial buffer?
@ -1034,7 +1018,7 @@ bool OV5640_Capture(uint8_t* buffer, uint32_t size)
dma_error = false;
dma_flags = 0;
TRACE_DEBUG("D");chThdSleep(TIME_MS2I(10));
/*
* Setup timer for PCLK
* Setup timer to trigger DMA in capture mode. On rising edge, we will
@ -1050,24 +1034,25 @@ bool OV5640_Capture(uint8_t* buffer, uint32_t size)
TIM8->CCER = TIM_CCER_CC1E;
capture_finished = false;
vsync = false;
vsync_cntr = 0;
I2C_Lock(); // Lock I2C because it uses the same DMA
while(!palReadLine(LINE_CAM_VSYNC)); // Wait for current picture to finish transmission
TRACE_DEBUG("G");chThdSleep(TIME_MS2I(10));
// Enable VSYNC interrupt
palSetLineCallback(LINE_CAM_VSYNC, (palcallback_t)vsync_cb, NULL);
palEnableLineEvent(LINE_CAM_VSYNC, PAL_EVENT_MODE_RISING_EDGE);
TRACE_DEBUG("H");chThdSleep(TIME_MS2I(10));
// Wait for capture to be finished
do {
TRACE_DEBUG("I");chThdSleep(TIME_MS2I(10));
chThdSleep(TIME_MS2I(10));
TRACE_DEBUG("dma_error=%08x dma_flags=%08x", dma_error, dma_flags);
} while(!capture_finished && !dma_error);
TRACE_DEBUG("J");chThdSleep(TIME_MS2I(10));
// Capture done, unlock I2C
I2C_Unlock();
TRACE_DEBUG("K");chThdSleep(TIME_MS2I(10));
if(dma_error)
{
if(dma_flags & STM32_DMA_ISR_HTIF) {
@ -1101,17 +1086,18 @@ bool OV5640_Capture(uint8_t* buffer, uint32_t size)
*/
void OV5640_InitGPIO(void)
{
palSetLineMode(LINE_CAM_PCLK, PAL_MODE_ALTERNATE(3) | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_XCLK, PAL_MODE_ALTERNATE(0) | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_PCLK, PAL_MODE_ALTERNATE(3));
palSetLineMode(LINE_CAM_VSYNC, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_XCLK, PAL_MODE_ALTERNATE(0));
palSetLineMode(LINE_CAM_D2, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D3, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D4, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D5, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D6, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D7, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D8, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_D9, PAL_MODE_INPUT | PAL_STM32_OSPEED_HIGHEST);
palSetPadMode(GPIOA, 8, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST);
palSetLineMode(LINE_CAM_EN, PAL_MODE_OUTPUT_PUSHPULL);
palSetLineMode(LINE_CAM_RESET, PAL_MODE_OUTPUT_PUSHPULL);
@ -1198,11 +1184,6 @@ void OV5640_SetResolution(resolution_t res)
I2C_write8_16bitreg(OV5640_I2C_ADR, OV5640_QSXGA2VGA[i].reg, OV5640_QSXGA2VGA[i].val);
break;
case RES_VGA_ZOOMED:
for(uint32_t i=0; (OV5640_QSXGA2VGA_ZOOMED[i].reg != 0xffff) || (OV5640_QSXGA2VGA_ZOOMED[i].val != 0xff); i++)
I2C_write8_16bitreg(OV5640_I2C_ADR, OV5640_QSXGA2VGA_ZOOMED[i].reg, OV5640_QSXGA2VGA_ZOOMED[i].val);
break;
case RES_XGA:
for(uint32_t i=0; (OV5640_QSXGA2XGA[i].reg != 0xffff) || (OV5640_QSXGA2XGA[i].val != 0xff); i++)
I2C_write8_16bitreg(OV5640_I2C_ADR, OV5640_QSXGA2XGA[i].reg, OV5640_QSXGA2XGA[i].val);

9
tracker/software/drivers/si446x.c
Wyświetl plik

@ -665,6 +665,7 @@ static void Si446x_shutdown(void)
static void lockRadio(void)
{
TRACE_DEBUG("LOCK");
// Initialize mutex
if(!radio_mtx_init)
chMtxObjectInit(&radio_mtx);
@ -672,16 +673,19 @@ static void lockRadio(void)
chMtxLock(&radio_mtx);
nextTransmissionWaiting = true;
TRACE_DEBUG("LOCKED1");
// Wait for old feeder thread to terminate
if(feeder_thd != NULL) // No waiting on first use
chThdWait(feeder_thd);
TRACE_DEBUG("LOCKED2");
}
void unlockRadio(void)
{
TRACE_DEBUG("UNLOCK");
nextTransmissionWaiting = false;
chMtxUnlock(&radio_mtx);
TRACE_DEBUG("UNLOCKED");
}
void lockRadioByCamera(void)
@ -1003,6 +1007,9 @@ THD_FUNCTION(si_fifo_feeder_afsk, arg)
// Free packet object memory
ax25_delete(pp);
TRACE_DEBUG("FIFO Feeder finished");
chThdExit(MSG_OK);
}

2
tracker/software/mcuconf.h
Wyświetl plik

@ -58,7 +58,7 @@
#define STM32_MCO1SEL STM32_MCO1SEL_PLL
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_PLL
#define STM32_MCO2PRE STM32_MCO2PRE_DIV2 /* Camera XCLK 24MHz */
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 /* Camera XCLK 24MHz */
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5

3
tracker/software/threads/radio/radio.c
Wyświetl plik

@ -45,6 +45,7 @@ void start_rx_thread(uint32_t freq, uint8_t rssi) {
bool transmitOnRadio(packet_t pp, uint32_t freq, uint8_t pwr, mod_t mod)
{
TRACE_DEBUG("A -------------------------------------------------");
if(freq == FREQ_APRS_DYNAMIC)
freq = getAPRSRegionFrequency(); // Get transmission frequency by geofencing
@ -80,6 +81,8 @@ bool transmitOnRadio(packet_t pp, uint32_t freq, uint8_t pwr, mod_t mod)
}
TRACE_DEBUG("B -------------------------------------------------");
return true;
}