micropython/ports
Nicko van Someren cfc212b108 rp2/rp2_dma: Introduce a new rp2.DMA class for control over DMA xfers.
This commit implements fairly complete support for the DMA controller in
the rp2 series of microcontrollers.  It provides a class for accessing the
DMA channels through a high-level, Pythonic interface, and functions for
setting and manipulating the DMA channel configurations.

Creating an instance of the rp2.DMA class claims one of the processor's DMA
channels.  A sensible, per-channel default value for the ctrl register can
be fetched from the DMA.pack_ctrl() function, and the components of this
register can be set via keyword arguments to pack_ctrl().

The read, write, count and ctrl attributes of the DMA class provide
read/write access to the respective registers of the DMA controller.  The
config() method allows any or all of these values to be set simultaneously
and adds a trigger keyword argument to allow the setup to immediately be
triggered.  The read and write attributes (or keywords in config()) accept
either actual addresses or any object that supports the buffer interface.
The active() method provides read/write control of the channel's activity,
allowing the user to start and stop the channel and test if it is running.

Standard MicroPython interrupt handlers are supported through the irq()
method and the channel can be released either by deleting it and allowing
it to be garbage-collected or with the explicit close() method.

Direct, unfettered access to the DMA controllers registers is provided
through a proxy memoryview() object returned by the DMA.registers attribute
that maps directly onto the memory-mapped registers.  This is necessary for
more fine-grained control and is helpful for allowing chaining of DMA
channels.

As a simple example, using DMA to do a fast memory copy just needs:

    src = bytearray(32*1024)
    dest = bytearray(32*1024)
    dma = rp2.DMA()
    dma.config(read=src, write=dest, count=len(src) // 4,
        ctrl=dma.pack_ctrl(), trigger=True)

    # Wait for completion
    while dma.active():
        pass

This API aims to strike a balance between simplicity and comprehensiveness.

Signed-off-by: Nicko van Someren <nicko@nicko.org>
Signed-off-by: Damien George <damien@micropython.org>
2023-12-22 13:04:51 +11:00
..
bare-arm
cc3200 ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
embed
esp32 ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
esp8266 ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
mimxrt ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
minimal ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
nrf nrf/main: Add /flash and /flash/lib to sys.path. 2023-12-22 11:15:19 +11:00
pic16bit ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
powerpc ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
qemu-arm ports: Switch build to use common lib/libm list of source files. 2023-12-08 15:42:41 +11:00
renesas-ra ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
rp2 rp2/rp2_dma: Introduce a new rp2.DMA class for control over DMA xfers. 2023-12-22 13:04:51 +11:00
samd ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
stm32 ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
unix ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
webassembly ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
windows ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00
zephyr ports: Fix sys.stdout.buffer.write() return value. 2023-12-22 10:32:46 +11:00