kopia lustrzana https://github.com/micropython/micropython
rp2/rp2_dma: Introduce a new rp2.DMA class for control over DMA xfers.
This commit implements fairly complete support for the DMA controller in
the rp2 series of microcontrollers. It provides a class for accessing the
DMA channels through a high-level, Pythonic interface, and functions for
setting and manipulating the DMA channel configurations.
Creating an instance of the rp2.DMA class claims one of the processor's DMA
channels. A sensible, per-channel default value for the ctrl register can
be fetched from the DMA.pack_ctrl() function, and the components of this
register can be set via keyword arguments to pack_ctrl().
The read, write, count and ctrl attributes of the DMA class provide
read/write access to the respective registers of the DMA controller. The
config() method allows any or all of these values to be set simultaneously
and adds a trigger keyword argument to allow the setup to immediately be
triggered. The read and write attributes (or keywords in config()) accept
either actual addresses or any object that supports the buffer interface.
The active() method provides read/write control of the channel's activity,
allowing the user to start and stop the channel and test if it is running.
Standard MicroPython interrupt handlers are supported through the irq()
method and the channel can be released either by deleting it and allowing
it to be garbage-collected or with the explicit close() method.
Direct, unfettered access to the DMA controllers registers is provided
through a proxy memoryview() object returned by the DMA.registers attribute
that maps directly onto the memory-mapped registers. This is necessary for
more fine-grained control and is helpful for allowing chaining of DMA
channels.
As a simple example, using DMA to do a fast memory copy just needs:
src = bytearray(32*1024)
dest = bytearray(32*1024)
dma = rp2.DMA()
dma.config(read=src, write=dest, count=len(src) // 4,
ctrl=dma.pack_ctrl(), trigger=True)
# Wait for completion
while dma.active():
pass
This API aims to strike a balance between simplicity and comprehensiveness.
Signed-off-by: Nicko van Someren <nicko@nicko.org>
Signed-off-by: Damien George <damien@micropython.org>
pull/13255/head
Nicko van Someren
Damien George
rodzic
e4d3ab3304
commit
cfc212b108
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@ -132,6 +132,7 @@ set(MICROPY_SOURCE_PORT
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pendsv.c
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rp2_flash.c
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rp2_pio.c
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rp2_dma.c
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uart.c
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usbd.c
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msc_disk.c
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@ -156,6 +157,7 @@ set(MICROPY_SOURCE_QSTR
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${MICROPY_PORT_DIR}/modos.c
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${MICROPY_PORT_DIR}/rp2_flash.c
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${MICROPY_PORT_DIR}/rp2_pio.c
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${MICROPY_PORT_DIR}/rp2_dma.c
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${CMAKE_BINARY_DIR}/pins_${MICROPY_BOARD}.c
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)
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@ -159,6 +159,7 @@ int main(int argc, char **argv) {
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readline_init0();
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machine_pin_init();
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rp2_pio_init();
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rp2_dma_init();
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machine_i2s_init0();
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#if MICROPY_PY_BLUETOOTH
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@ -207,6 +208,7 @@ int main(int argc, char **argv) {
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#if MICROPY_PY_NETWORK
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mod_network_deinit();
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#endif
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rp2_dma_deinit();
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rp2_pio_deinit();
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#if MICROPY_PY_BLUETOOTH
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mp_bluetooth_deinit();
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@ -88,6 +88,7 @@ STATIC const mp_rom_map_elem_t rp2_module_globals_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_Flash), MP_ROM_PTR(&rp2_flash_type) },
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{ MP_ROM_QSTR(MP_QSTR_PIO), MP_ROM_PTR(&rp2_pio_type) },
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{ MP_ROM_QSTR(MP_QSTR_StateMachine), MP_ROM_PTR(&rp2_state_machine_type) },
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{ MP_ROM_QSTR(MP_QSTR_DMA), MP_ROM_PTR(&rp2_dma_type) },
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{ MP_ROM_QSTR(MP_QSTR_bootsel_button), MP_ROM_PTR(&rp2_bootsel_button_obj) },
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#if MICROPY_PY_NETWORK_CYW43
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@ -31,8 +31,12 @@
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extern const mp_obj_type_t rp2_flash_type;
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extern const mp_obj_type_t rp2_pio_type;
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extern const mp_obj_type_t rp2_state_machine_type;
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extern const mp_obj_type_t rp2_dma_type;
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void rp2_pio_init(void);
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void rp2_pio_deinit(void);
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void rp2_dma_init(void);
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void rp2_dma_deinit(void);
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#endif // MICROPY_INCLUDED_RP2_MODRP2_H
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@ -0,0 +1,469 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Nicko van Someren
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <string.h>
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#include "py/runtime.h"
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#include "py/mperrno.h"
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#include "py/objarray.h"
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#include "shared/runtime/mpirq.h"
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#include "modrp2.h"
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#include "hardware/irq.h"
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#include "hardware/dma.h"
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#define CHANNEL_CLOSED 0xff
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typedef struct _rp2_dma_ctrl_obj_t {
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mp_obj_base_t base;
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uint32_t value;
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} rp2_dma_config_obj_t;
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typedef struct _rp2_dma_obj_t {
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mp_obj_base_t base;
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uint8_t channel;
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uint8_t irq_flag : 1;
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uint8_t irq_trigger : 1;
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} rp2_dma_obj_t;
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typedef struct _rp2_dma_ctrl_field_t {
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qstr name;
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uint8_t shift : 5;
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uint8_t length : 3;
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uint8_t read_only : 1;
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} rp2_dma_ctrl_field_t;
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STATIC rp2_dma_ctrl_field_t rp2_dma_ctrl_fields_table[] = {
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{ MP_QSTR_enable, 0, 1, 0 },
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{ MP_QSTR_high_pri, 1, 1, 0 },
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{ MP_QSTR_size, 2, 2, 0 },
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{ MP_QSTR_inc_read, 4, 1, 0 },
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{ MP_QSTR_inc_write, 5, 1, 0 },
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{ MP_QSTR_ring_size, 6, 4, 0 },
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{ MP_QSTR_ring_sel, 10, 1, 0 },
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{ MP_QSTR_chain_to, 11, 4, 0 },
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{ MP_QSTR_treq_sel, 15, 6, 0 },
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{ MP_QSTR_irq_quiet, 21, 1, 0 },
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{ MP_QSTR_bswap, 22, 1, 0 },
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{ MP_QSTR_sniff_en, 23, 1, 0 },
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{ MP_QSTR_busy, 24, 1, 1 },
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// bits 25 through 28 are reserved
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{ MP_QSTR_write_err, 29, 1, 0 },
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{ MP_QSTR_read_err, 30, 1, 0 },
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{ MP_QSTR_ahb_err, 31, 1, 1 },
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};
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STATIC const uint32_t rp2_dma_ctrl_field_count = MP_ARRAY_SIZE(rp2_dma_ctrl_fields_table);
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#define REG_TYPE_COUNT 0 // Accept just integers
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#define REG_TYPE_CONF 1 // Accept integers or ctrl values
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#define REG_TYPE_ADDR_READ 2 // Accept integers, buffers or objects that can be read from
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#define REG_TYPE_ADDR_WRITE 3 // Accept integers, buffers or objects that can be written to
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STATIC uint32_t rp2_dma_register_value_from_obj(mp_obj_t o, int reg_type) {
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if (reg_type == REG_TYPE_ADDR_READ || reg_type == REG_TYPE_ADDR_WRITE) {
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mp_buffer_info_t buf_info;
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mp_uint_t flags = MP_BUFFER_READ;
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if (mp_get_buffer(o, &buf_info, flags)) {
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return (uint32_t)buf_info.buf;
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}
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}
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return mp_obj_get_int_truncated(o);
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}
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STATIC void rp2_dma_irq_handler(void) {
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// Main IRQ handler
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uint32_t irq_bits = dma_hw->ints0;
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dma_hw->ints0 = 0xffff;
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for (int i = 0; i < NUM_DMA_CHANNELS; i++) {
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if (irq_bits & (1u << i)) {
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mp_irq_obj_t *handler = MP_STATE_PORT(rp2_dma_irq_obj[i]);
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if (handler) {
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rp2_dma_obj_t *self = (rp2_dma_obj_t *)handler->parent;
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self->irq_flag = 1;
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mp_irq_handler(handler);
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} else {
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// We got an interrupt with no handler. Disable the channel
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dma_channel_set_irq0_enabled(i, false);
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}
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}
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}
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}
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STATIC mp_uint_t rp2_dma_irq_trigger(mp_obj_t self_in, mp_uint_t new_trigger) {
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rp2_dma_obj_t *self = MP_OBJ_TO_PTR(self_in);
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irq_set_enabled(DMA_IRQ_0, false);
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self->irq_flag = 0;
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dma_channel_set_irq0_enabled(self->channel, (new_trigger != 0));
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irq_set_enabled(DMA_IRQ_0, true);
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return 0;
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}
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STATIC mp_uint_t rp2_dma_irq_info(mp_obj_t self_in, mp_uint_t info_type) {
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rp2_dma_obj_t *self = MP_OBJ_TO_PTR(self_in);
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if (info_type == MP_IRQ_INFO_FLAGS) {
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return self->irq_flag;
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} else if (info_type == MP_IRQ_INFO_TRIGGERS) {
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return (dma_hw->ints0 & (1u << self->channel)) != 0;
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}
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return 0;
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}
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STATIC const mp_irq_methods_t rp2_dma_irq_methods = {
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.trigger = rp2_dma_irq_trigger,
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.info = rp2_dma_irq_info,
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};
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STATIC mp_obj_t rp2_dma_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
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mp_arg_check_num(n_args, n_kw, 0, 0, false);
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int dma_channel = dma_claim_unused_channel(false);
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if (dma_channel < 0) {
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mp_raise_OSError(MP_EBUSY);
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}
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rp2_dma_obj_t *self = m_new_obj_with_finaliser(rp2_dma_obj_t);
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self->base.type = &rp2_dma_type;
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self->channel = dma_channel;
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// Return the DMA object.
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return MP_OBJ_FROM_PTR(self);
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}
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STATIC void rp2_dma_error_if_closed(rp2_dma_obj_t *self) {
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if (self->channel == CHANNEL_CLOSED) {
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mp_raise_ValueError(MP_ERROR_TEXT("channel closed"));
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}
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}
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STATIC void rp2_dma_attr(mp_obj_t self_in, qstr attr_in, mp_obj_t *dest) {
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rp2_dma_obj_t *self = MP_OBJ_TO_PTR(self_in);
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if (dest[0] == MP_OBJ_NULL) {
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// Load attribute
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dma_channel_hw_t *reg_block = dma_channel_hw_addr(self->channel);
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if (attr_in == MP_QSTR_read) {
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rp2_dma_error_if_closed(self);
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dest[0] = mp_obj_new_int_from_uint((mp_uint_t)reg_block->read_addr);
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} else if (attr_in == MP_QSTR_write) {
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rp2_dma_error_if_closed(self);
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dest[0] = mp_obj_new_int_from_uint((mp_uint_t)reg_block->write_addr);
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} else if (attr_in == MP_QSTR_count) {
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rp2_dma_error_if_closed(self);
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dest[0] = mp_obj_new_int_from_uint((mp_uint_t)reg_block->transfer_count);
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} else if (attr_in == MP_QSTR_ctrl) {
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rp2_dma_error_if_closed(self);
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dest[0] = mp_obj_new_int_from_uint((mp_uint_t)reg_block->al1_ctrl);
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} else if (attr_in == MP_QSTR_channel) {
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dest[0] = mp_obj_new_int_from_uint(self->channel);
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} else if (attr_in == MP_QSTR_registers) {
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mp_obj_array_t *reg_view = m_new_obj(mp_obj_array_t);
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mp_obj_memoryview_init(reg_view, 'I' | MP_OBJ_ARRAY_TYPECODE_FLAG_RW, 0, 16, dma_channel_hw_addr(self->channel));
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dest[0] = reg_view;
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} else {
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// Continue attribute search in locals dict.
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dest[1] = MP_OBJ_SENTINEL;
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}
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} else {
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// Set or delete attribute
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if (dest[1] == MP_OBJ_NULL) {
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// We don't support deleting attributes.
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return;
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}
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rp2_dma_error_if_closed(self);
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if (attr_in == MP_QSTR_read) {
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uint32_t value = rp2_dma_register_value_from_obj(dest[1], REG_TYPE_ADDR_READ);
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dma_channel_set_read_addr(self->channel, (volatile void *)value, false);
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dest[0] = MP_OBJ_NULL; // indicate success
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} else if (attr_in == MP_QSTR_write) {
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uint32_t value = rp2_dma_register_value_from_obj(dest[1], REG_TYPE_ADDR_WRITE);
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dma_channel_set_write_addr(self->channel, (volatile void *)value, false);
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dest[0] = MP_OBJ_NULL; // indicate success
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} else if (attr_in == MP_QSTR_count) {
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uint32_t value = rp2_dma_register_value_from_obj(dest[1], REG_TYPE_COUNT);
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dma_channel_set_trans_count(self->channel, value, false);
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dest[0] = MP_OBJ_NULL; // indicate success
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} else if (attr_in == MP_QSTR_ctrl) {
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uint32_t value = rp2_dma_register_value_from_obj(dest[1], REG_TYPE_CONF);
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dma_channel_set_config(self->channel, (dma_channel_config *)&value, false);
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dest[0] = MP_OBJ_NULL; // indicate success
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}
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}
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}
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STATIC void rp2_dma_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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rp2_dma_obj_t *self = MP_OBJ_TO_PTR(self_in);
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mp_printf(print, "DMA(%u)", self->channel);
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}
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// DMA.config(*, read, write, count, ctrl, trigger)
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STATIC mp_obj_t rp2_dma_config(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
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rp2_dma_obj_t *self = MP_OBJ_TO_PTR(*pos_args);
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rp2_dma_error_if_closed(self);
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enum {
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ARG_read,
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ARG_write,
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ARG_count,
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ARG_ctrl,
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ARG_trigger,
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};
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_read, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
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{ MP_QSTR_write, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
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{ MP_QSTR_count, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
|
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{ MP_QSTR_ctrl, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
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{ MP_QSTR_trigger, MP_ARG_KW_ONLY | MP_ARG_BOOL, {.u_bool = false} },
|
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};
|
||||
|
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
|
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// Don't include self in arg parsing
|
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mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
|
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// We only do anything if there was at least one argument
|
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if (kw_args->used) {
|
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bool trigger = args[ARG_trigger].u_bool;
|
||||
mp_int_t value_count = trigger ? kw_args->used - 1 : kw_args->used;
|
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if (trigger && (value_count == 0)) {
|
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// Only a "true" trigger was passed; just start a transfer
|
||||
dma_channel_start(self->channel);
|
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} else {
|
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if (args[ARG_read].u_obj != MP_OBJ_NULL) {
|
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uint32_t value = rp2_dma_register_value_from_obj(args[ARG_read].u_obj, REG_TYPE_ADDR_READ);
|
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value_count--;
|
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dma_channel_set_read_addr(self->channel, (volatile void *)value, trigger && (value_count == 0));
|
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}
|
||||
if (args[ARG_write].u_obj != MP_OBJ_NULL) {
|
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uint32_t value = rp2_dma_register_value_from_obj(args[ARG_write].u_obj, REG_TYPE_ADDR_WRITE);
|
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value_count--;
|
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dma_channel_set_write_addr(self->channel, (volatile void *)value, trigger && (value_count == 0));
|
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}
|
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if (args[ARG_count].u_obj != MP_OBJ_NULL) {
|
||||
uint32_t value = rp2_dma_register_value_from_obj(args[ARG_count].u_obj, REG_TYPE_COUNT);
|
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value_count--;
|
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dma_channel_set_trans_count(self->channel, value, trigger && (value_count == 0));
|
||||
}
|
||||
if (args[ARG_ctrl].u_obj != MP_OBJ_NULL) {
|
||||
uint32_t value = rp2_dma_register_value_from_obj(args[ARG_ctrl].u_obj, REG_TYPE_CONF);
|
||||
value_count--;
|
||||
dma_channel_set_config(self->channel, (dma_channel_config *)&value, trigger && (value_count == 0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return mp_const_none;
|
||||
}
|
||||
STATIC MP_DEFINE_CONST_FUN_OBJ_KW(rp2_dma_config_obj, 1, rp2_dma_config);
|
||||
|
||||
// DMA.active([value])
|
||||
STATIC mp_obj_t rp2_dma_active(size_t n_args, const mp_obj_t *args) {
|
||||
rp2_dma_obj_t *self = MP_OBJ_TO_PTR(args[0]);
|
||||
rp2_dma_error_if_closed(self);
|
||||
|
||||
if (n_args > 1) {
|
||||
if (mp_obj_is_true(args[1])) {
|
||||
dma_channel_start(self->channel);
|
||||
} else {
|
||||
dma_channel_abort(self->channel);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t busy = dma_channel_is_busy(self->channel);
|
||||
return mp_obj_new_bool((mp_int_t)busy);
|
||||
}
|
||||
STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(rp2_dma_active_obj, 1, 2, rp2_dma_active);
|
||||
|
||||
// Default is quiet, unpaced, read and write incrementing, word transfers, enabled
|
||||
#define DEFAULT_DMA_CONFIG (1 << 21) | (0x3f << 15) | (1 << 5) | (1 << 4) | (2 << 2) | (1 << 0)
|
||||
|
||||
// DMA.pack_ctrl(...)
|
||||
STATIC mp_obj_t rp2_dma_pack_ctrl(size_t n_pos_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
|
||||
// Pack keyword settings into a control register value, using either the default for this
|
||||
// DMA channel or the provided defaults
|
||||
rp2_dma_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
|
||||
mp_uint_t value = DEFAULT_DMA_CONFIG | ((self->channel & 0xf) << 11);
|
||||
|
||||
if (n_pos_args > 1) {
|
||||
mp_raise_TypeError(MP_ERROR_TEXT("pack_ctrl only takes keyword arguments"));
|
||||
}
|
||||
mp_uint_t remaining = kw_args->used;
|
||||
|
||||
mp_map_elem_t *default_entry = mp_map_lookup(kw_args, MP_OBJ_NEW_QSTR(MP_QSTR_default), MP_MAP_LOOKUP);
|
||||
if (default_entry) {
|
||||
remaining--;
|
||||
value = mp_obj_get_int_truncated(default_entry->value);
|
||||
}
|
||||
|
||||
for (mp_uint_t i = 0; i < rp2_dma_ctrl_field_count; i++) {
|
||||
mp_map_elem_t *field_entry = mp_map_lookup(
|
||||
kw_args,
|
||||
MP_OBJ_NEW_QSTR(rp2_dma_ctrl_fields_table[i].name),
|
||||
MP_MAP_LOOKUP
|
||||
);
|
||||
if (field_entry) {
|
||||
remaining--;
|
||||
// Silently ignore read-only fields, to allow the passing of a modified unpack_ctrl() results
|
||||
if (!rp2_dma_ctrl_fields_table[i].read_only) {
|
||||
mp_uint_t field_value = mp_obj_get_int_truncated(field_entry->value);
|
||||
mp_uint_t mask = ((1 << rp2_dma_ctrl_fields_table[i].length) - 1);
|
||||
mp_uint_t masked_value = field_value & mask;
|
||||
if (field_value != masked_value) {
|
||||
mp_raise_ValueError(MP_ERROR_TEXT("bad field value"));
|
||||
}
|
||||
value &= ~(mask << rp2_dma_ctrl_fields_table[i].shift);
|
||||
value |= masked_value << rp2_dma_ctrl_fields_table[i].shift;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (remaining) {
|
||||
mp_raise_TypeError(NULL);
|
||||
}
|
||||
|
||||
return mp_obj_new_int_from_uint(value);
|
||||
}
|
||||
STATIC MP_DEFINE_CONST_FUN_OBJ_KW(rp2_dma_pack_ctrl_obj, 1, rp2_dma_pack_ctrl);
|
||||
|
||||
// DMA.unpack_ctrl(value)
|
||||
STATIC mp_obj_t rp2_dma_unpack_ctrl(mp_obj_t value_obj) {
|
||||
// Return a dict representing the unpacked fields of a control register value
|
||||
mp_obj_t result_dict[rp2_dma_ctrl_field_count * 2];
|
||||
|
||||
mp_uint_t value = mp_obj_get_int_truncated(value_obj);
|
||||
|
||||
for (mp_uint_t i = 0; i < rp2_dma_ctrl_field_count; i++) {
|
||||
result_dict[i * 2] = MP_OBJ_NEW_QSTR(rp2_dma_ctrl_fields_table[i].name);
|
||||
mp_uint_t field_value =
|
||||
(value >> rp2_dma_ctrl_fields_table[i].shift) & ((1 << rp2_dma_ctrl_fields_table[i].length) - 1);
|
||||
result_dict[i * 2 + 1] = MP_OBJ_NEW_SMALL_INT(field_value);
|
||||
}
|
||||
|
||||
return mp_obj_dict_make_new(&mp_type_dict, 0, rp2_dma_ctrl_field_count, result_dict);
|
||||
}
|
||||
STATIC MP_DEFINE_CONST_FUN_OBJ_1(rp2_dma_unpack_ctrl_fun_obj, rp2_dma_unpack_ctrl);
|
||||
STATIC MP_DEFINE_CONST_STATICMETHOD_OBJ(rp2_dma_unpack_ctrl_obj, MP_ROM_PTR(&rp2_dma_unpack_ctrl_fun_obj));
|
||||
|
||||
STATIC mp_obj_t rp2_dma_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
|
||||
enum { ARG_handler, ARG_hard };
|
||||
static const mp_arg_t allowed_args[] = {
|
||||
{ MP_QSTR_handler, MP_ARG_OBJ, {.u_rom_obj = mp_const_none} },
|
||||
{ MP_QSTR_hard, MP_ARG_BOOL, {.u_bool = false} },
|
||||
};
|
||||
|
||||
// Parse the arguments.
|
||||
rp2_dma_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
|
||||
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
|
||||
mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
|
||||
|
||||
// Get the IRQ object.
|
||||
mp_irq_obj_t *irq = MP_STATE_PORT(rp2_dma_irq_obj[self->channel]);
|
||||
|
||||
// Allocate the IRQ object if it doesn't already exist.
|
||||
if (irq == NULL) {
|
||||
irq = mp_irq_new(&rp2_dma_irq_methods, MP_OBJ_FROM_PTR(self));
|
||||
MP_STATE_PORT(rp2_dma_irq_obj[self->channel]) = irq;
|
||||
}
|
||||
|
||||
if (n_args > 1 || kw_args->used != 0) {
|
||||
// Disable all IRQs while data is updated.
|
||||
irq_set_enabled(DMA_IRQ_0, false);
|
||||
|
||||
// Update IRQ data.
|
||||
irq->handler = args[ARG_handler].u_obj;
|
||||
irq->ishard = args[ARG_hard].u_bool;
|
||||
self->irq_flag = 0;
|
||||
|
||||
// Enable IRQ if a handler is given.
|
||||
bool enable = (args[ARG_handler].u_obj != mp_const_none);
|
||||
dma_channel_set_irq0_enabled(self->channel, enable);
|
||||
|
||||
irq_set_enabled(DMA_IRQ_0, true);
|
||||
}
|
||||
|
||||
return MP_OBJ_FROM_PTR(irq);
|
||||
}
|
||||
STATIC MP_DEFINE_CONST_FUN_OBJ_KW(rp2_dma_irq_obj, 1, rp2_dma_irq);
|
||||
|
||||
// DMA.close()
|
||||
STATIC mp_obj_t rp2_dma_close(mp_obj_t self_in) {
|
||||
rp2_dma_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
||||
uint8_t channel = self->channel;
|
||||
|
||||
if (channel != CHANNEL_CLOSED) {
|
||||
// Clean up interrupt handler to ensure garbage collection
|
||||
mp_irq_obj_t *irq = MP_STATE_PORT(rp2_dma_irq_obj[channel]);
|
||||
MP_STATE_PORT(rp2_dma_irq_obj[channel]) = MP_OBJ_NULL;
|
||||
if (irq) {
|
||||
irq->parent = MP_OBJ_NULL;
|
||||
irq->handler = MP_OBJ_NULL;
|
||||
dma_channel_set_irq0_enabled(channel, false);
|
||||
}
|
||||
dma_channel_unclaim(channel);
|
||||
self->channel = CHANNEL_CLOSED;
|
||||
}
|
||||
|
||||
return mp_const_none;
|
||||
}
|
||||
STATIC MP_DEFINE_CONST_FUN_OBJ_1(rp2_dma_close_obj, rp2_dma_close);
|
||||
|
||||
STATIC const mp_rom_map_elem_t rp2_dma_locals_dict_table[] = {
|
||||
{ MP_ROM_QSTR(MP_QSTR_config), MP_ROM_PTR(&rp2_dma_config_obj) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_active), MP_ROM_PTR(&rp2_dma_active_obj) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_irq), MP_ROM_PTR(&rp2_dma_irq_obj) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_close), MP_ROM_PTR(&rp2_dma_close_obj) },
|
||||
{ MP_ROM_QSTR(MP_QSTR___del__), MP_ROM_PTR(&rp2_dma_close_obj) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_pack_ctrl), MP_ROM_PTR(&rp2_dma_pack_ctrl_obj) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_unpack_ctrl), MP_ROM_PTR(&rp2_dma_unpack_ctrl_obj) },
|
||||
};
|
||||
STATIC MP_DEFINE_CONST_DICT(rp2_dma_locals_dict, rp2_dma_locals_dict_table);
|
||||
|
||||
MP_DEFINE_CONST_OBJ_TYPE(
|
||||
rp2_dma_type,
|
||||
MP_QSTR_DMA,
|
||||
MP_TYPE_FLAG_NONE,
|
||||
make_new, rp2_dma_make_new,
|
||||
print, rp2_dma_print,
|
||||
attr, rp2_dma_attr,
|
||||
locals_dict, &rp2_dma_locals_dict
|
||||
);
|
||||
|
||||
void rp2_dma_init(void) {
|
||||
// Set up interrupts.
|
||||
memset(MP_STATE_PORT(rp2_dma_irq_obj), 0, sizeof(MP_STATE_PORT(rp2_dma_irq_obj)));
|
||||
irq_set_exclusive_handler(DMA_IRQ_0, rp2_dma_irq_handler);
|
||||
}
|
||||
|
||||
void rp2_dma_deinit(void) {
|
||||
// Disable and clear interrupts.
|
||||
irq_set_mask_enabled(1u << DMA_IRQ_0, false);
|
||||
irq_remove_handler(DMA_IRQ_0, rp2_dma_irq_handler);
|
||||
}
|
||||
|
||||
MP_REGISTER_ROOT_POINTER(void *rp2_dma_irq_obj[NUM_DMA_CHANNELS]);
|
||||
Ładowanie…
Reference in New Issue