kopia lustrzana https://github.com/gnea/grbl
91 wiersze
2.6 KiB
C
91 wiersze
2.6 KiB
C
/*
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config.h - compile time configuration
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Part of Grbl
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Copyright (c) 2009-2011 Simen Svale Skogsrud
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Grbl is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Grbl is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Grbl. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef config_h
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#define config_h
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#define BAUD_RATE 9600
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// Updated default pin-assignments from 0.6 onwards
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// (see bottom of file for a copy of the old config)
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#define STEPPERS_DISABLE_DDR DDRB
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#define STEPPERS_DISABLE_PORT PORTB
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#define STEPPERS_DISABLE_BIT 0
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#define STEPPING_DDR DDRD
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#define STEPPING_PORT PORTD
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#define X_STEP_BIT 2
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#define Y_STEP_BIT 3
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#define Z_STEP_BIT 4
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#define X_DIRECTION_BIT 5
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#define Y_DIRECTION_BIT 6
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#define Z_DIRECTION_BIT 7
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#define LIMIT_DDR DDRB
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#define LIMIT_PIN PINB
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#define X_LIMIT_BIT 1
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#define Y_LIMIT_BIT 2
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#define Z_LIMIT_BIT 3
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#define SPINDLE_ENABLE_DDR DDRB
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#define SPINDLE_ENABLE_PORT PORTB
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#define SPINDLE_ENABLE_BIT 4
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#define SPINDLE_DIRECTION_DDR DDRB
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#define SPINDLE_DIRECTION_PORT PORTB
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#define SPINDLE_DIRECTION_BIT 5
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// The temporal resolution of the acceleration management subsystem. Higher number
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// give smoother acceleration but may impact performance
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#define ACCELERATION_TICKS_PER_SECOND 40L
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#endif
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// Pin-assignments from Grbl 0.5
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// #define STEPPERS_DISABLE_DDR DDRD
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// #define STEPPERS_DISABLE_PORT PORTD
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// #define STEPPERS_DISABLE_BIT 2
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//
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// #define STEPPING_DDR DDRC
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// #define STEPPING_PORT PORTC
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// #define X_STEP_BIT 0
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// #define Y_STEP_BIT 1
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// #define Z_STEP_BIT 2
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// #define X_DIRECTION_BIT 3
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// #define Y_DIRECTION_BIT 4
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// #define Z_DIRECTION_BIT 5
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//
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// #define LIMIT_DDR DDRD
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// #define LIMIT_PORT PORTD
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// #define X_LIMIT_BIT 3
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// #define Y_LIMIT_BIT 4
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// #define Z_LIMIT_BIT 5
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//
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// #define SPINDLE_ENABLE_DDR DDRD
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// #define SPINDLE_ENABLE_PORT PORTD
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// #define SPINDLE_ENABLE_BIT 6
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//
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// #define SPINDLE_DIRECTION_DDR DDRD
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// #define SPINDLE_DIRECTION_PORT PORTD
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// #define SPINDLE_DIRECTION_BIT 7
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